Simulation to Silicon: A Unified Concurrency Abstraction for Portable Verification Testbenches

Abstract

Transaction-level System-on-Chip (SoC) verification testbenches increasingly need to operate across heterogeneous execution platforms, including event-driven SystemVerilog simulation and thread-based emulation or virtual prototyping environments. However, concurrency in verification environments is typically expressed using platform-specific mechanisms, such as fork–join constructs in simulations or operating-system threads in emulation, often leading to duplicated testbench implementations and refactoring when transitioning between platforms. This paper presents a lightweight, platform-independent concurrency abstraction that enables a single verification testbench source code to be executed consistently across SystemVerilog simulation and C/C++-based emulation environments. The approach elevates concurrency to an explicit, user-visible abstraction with well-defined semantics and decouples the verification intent from platform-specific scheduling mechanisms. A unified concurrency interface is realized through runtime polymorphism, binding to SystemVerilog processes via the Direct Programming Interface (DPI) in simulation and to POSIX threads in emulation. The framework is evaluated across multiple interface environments, including Universal Serial Bus (USB), Advanced eXtensible Interface (AXI), Mobile Industry Processor Interface Display Serial Interface 2 (MIPI DSI-2), and Universal Asynchronous Receiver-Transmitter (UART) transactors. The experimental results demonstrate transaction-level functional equivalence across simulation and emulation platforms, substantial reductions in testbench code duplication, particularly in highly concurrent environments, and low runtime overhead, with abstraction mechanism cost remaining under 1% for most evaluated protocols and reaching 3.6% in the most synchronization-intensive workload (AXI). These results show that a portable concurrency abstraction can significantly improve verification productivity while preserving correctness and incurring low runtime overhead.