G-Power, an architecture-level GPU power modeling framework that utilizes additional known GPU chips to provide additional knowledge and adopts a three-phase algorithm consisting of pre-training with additional known chips, attention-inspired aggregation, and fine-tuning on the target GPU.
Abstract
Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has become an important design objective for modern GPUs. GPU power optimization relies on fast power evaluation, requiring architecture-level GPU power model. However, because of the time-consuming power label collection, only simple microbenchmarks are adopted for training. The limitation of microbenchmarks as training data incurs low accuracy for existing architecture-level GPU power models like AccelWattch. To address the limitation of microbenchmarks as training data, we propose G-Power, an architecture-level GPU power modeling framework that utilizes additional known GPU chips to provide additional knowledge. G-Power utilizes the aggregated knowledge foundation from additional known GPU chips and then performs fine-tuning on our target GPU. To provide foundations with additional known GPU chips and capture the similarity to utilize these foundations for fine-tuning, G-Power adopts a three-phase algorithm consisting of 1) pre-training with additional known chips, 2) attention-inspired aggregation, and 3) fine-tuning on our target GPU. We evaluate G-Power on four modern NVIDIA GPUs, demonstrating high accuracy. G-Power can achieve a low MAPE of 14% and a high correlation coefficient R of 0.88 on average, which are 22% lower MAPE and 0.36 higher R than AccelWattch.
SA-Scheduler is presented, a structure-derived bottleneck-aware scheduling framework for multitasking MCM-GPUs that determines chip placement without hardware modification or runtime bottleneck profiling, and provides a principled and scalable foundation for multitasking on future MCM-GPUs.
Tie-Jian Zhang, Guangda Zhang, Lu Wang et al.· ACM Transactions on Design A...· 0 citations
With the ever-growing size of deep learning models, GPU memory is prone to being insufficient during training. A prominent approach is ZeRO-Offload, which moves the optimizer states to CPU memory and performs parameter update using CPU. However, the deficiencies of ZeRO-Offload include low GPU utilization, imperfect ov...
Zhi-Yi Yao, Zu-Ning Liang, Yue-Dong Xu et al.· 0 citations
This paper presents the first GPU-accelerated gate-level time-based power analysis framework, and proposes a novel data structure to enable efficient state-dependent power retrieval to enable efficient state-dependent power retrieval.
Wei-Hao Wang, Yikang Ouyang, Hong-Yuan Liu et al.· ACM Transactions on Architec...· 0 citations
Experiments conducted on a real heterogeneous CPU-GPU cluster using diverse GPU workloads demonstrate that the performance of the GDSF computing framework and its scheduling algorithms meets the expected research objectives, thus validating the feasibility and effectiveness of the proposed design.
Qin-Lu He, Fan Zhang, Gen-Qing Bian et al.· Cluster Computing· 0 citations
This project analyzes how the architectural changes introduced across NVIDIA’s Volta, Ampere, and Hopper GPU generations translate into real-world performance and energy efficiency gains and shows that specialization can deliver substantial performance and efficiency gains, but only when workloads can effectively use t...
Matthew Tindale, I. Karlin, Tobias Salamon et al.· Inquiry@Queen's Undergraduat...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.