Timing Analysis of Ethernet 10BASE-T1S

Abstract

BASE-T1S is a low-cost multidrop Ethernet technology whose shared-medium access is governed by Physical Layer Collision Avoidance (PLCA). While attractive for automotive zonal edge networks, PLCA introduces non-trivial bus-access latency whose worst case depends on the interaction of roundrobin arbitration, empty and occupied transmit opportunities, node ordering, burst behavior, and heterogeneous traffic releases. To the best of our knowledge, this is the first paper devoted to a formal worst-case timing analysis of Ethernet 10BASE-T1S at the base PLCA MAC/PHY arbitration layer. Unlike classical algebraic analyses used for protocols such as CAN, FlexRay, or switched Ethernet, we model 10BASE-T1S as a network of timed automata and use Uppaal model checking to compute guaranteed upper bounds on protocol-level packet delays. The method also yields witness traces that explain how pathological worst-case scenarios arise, making it useful for timing debugging and design-space exploration. Our results complement simulation by isolating the contribution of PLCA itself and by exposing valid worst-case schedules that finite simulation runs may miss.