Workload-Aware Compressor Tree Design Automation With Statistical Calibration for Efficient AI Accelerators

Abstract

A compressor tree is an essential building block of multiply-and-accumulate (MAC) units, hierarchically reducing multiple partial sums without immediate carry propagation. This article introduces a workload-aware compressor tree synthesis framework that aligns model-level noise tolerance with hardware-level arithmetic design to enable statistically guided MAC in artificial intelligence (AI) accelerators. Unlike conventional compressor trees that rely on uniform approximation policies, the proposed approach derives an allowable error budget by analyzing noise–accuracy behavior and profiling workload-specific bit-pattern distributions, revealing that most significant bit (MSB) regions are biased toward high-Hamming-weight values, such as all-ones and near-all-ones cases. Guided by these statistics, the framework automatically selects among exact and approximate compressors from a characterization library, and incorporates a pattern-accurate 6:3 compressor designed to minimize MSB-sensitive error while preserving hardware efficiency. This unified flow generates compressor trees that remain compliant with model-derived accuracy constraints while significantly reducing cost. Fabricated in a commercial 28 nm process, the resulting designs improve delay and power by up to 15%–25% across diverse convolutional neural network (CNN) and Transformer models, achieving 14–27 TOPS/W while maintaining only 0.07% average inference accuracy degradation. These results highlight that workload-calibrated accumulation is a critical optimization axis for modern AI accelerators and demonstrate the value of statistically specialized compressor structures for domain-specific edge inference accelerator deployments.