Design and Implementation of a Compute-In-Memory SRAM with On-Chip MAC for Low-Power Edge Computing

Abstract

Different methods have been suggested to solve the critical limitations encountered in the Von Neumann architecture: the continuous transfer of data between the memory and the processing units, leading to an increase in energy consumption and latency. This paper presents a digital design of multiply-accumulation (MAC) embedded within a standard 6T SRAM block using Verilog HDL. The design multiplies input data with corresponding weights that are stored in memory and accumulates the results to perform the fundamental calculations needed for neural network inference. It functions as a single-layer neural network and can carry out effective dot-product operations for tasks involving light AI inference. The proposed design combines a custom MAC computation engine with a 64KB SRAM that runs on a Spartan 6 XC6SLX150-3CSG484 FPGA which supports configurable vector lengths and operates as a single-layer neural network accelerator for lightweight AI tasks. In comparison to traditional SRAM-based processing, experimental results show a sustained throughput of 7.7 M MAC/s with an energy efficiency of 0.125 nJ/MAC, achieving energy efficiency. The design makes it easier to integrate with post-processing steps like activation functions by directly storing computation results in on-chip memory and exporting them to CSV for additional processing. A small, low-power solution for real-time AI workloads in embedded and Internet of Things devices is offered by this CIM technique.