System-Level Optimization and Co-Design of the SM4 Algorithm for RISC-V

Abstract

In response to issues such as high computational latency and excessive energy consumption encountered when implementing the SM4 algorithm on general-purpose RISC-V processors, this paper proposes an assembly-level system optimization and hardware-software co-design scheme tailored for the RISC-V platform. Optimization is conducted at both the instruction level and the architectural level. First, memory access operations and inter-instruction dependencies are reduced through techniques including S-box lookup table reuse, shift-XOR instruction reordering, and lightweight pipelining. Next, modular assembly implementations are developed for the T-transformation, T′-transformation, and key expansion, with unified register conventions and calling interfaces established. Then, register rotation and loop unrolling mechanisms are introduced to enhance data reuse and lower control overhead. Finally, a hardware-friendly instruction sequence and interface specification are designed to facilitate smooth migration to custom instructions or coprocessor extensions in the future. Experimental results show that, compared to the C implementation, the optimized assembly version reduces the total instruction count by 37.5% and the cycle count by 54.2%, yielding an overall performance gain of 2.2-fold. Notably, the efficiency of the T′-transformation improves by nearly 3.9-fold. Without additional hardware cost, the proposed approach significantly boosts the execution efficiency of SM4 on RISC-V. It thus provides a systematic optimization path for embedded cryptographic implementations that ensures performance, scalability, and portability.