Jul 2026· GECCO Companion· pp. 1212-1219· 0 citations· 13 references
Computer Science
TL;DR
A unified ACS2 framework for comparing five execution regimes: a symbolic baseline, single-process CPU execution, multiprocessing CPU execution, sequential independently seeded tensorized GPU execution, and the same PyTorch tensor backend executed on the host CPU.
Abstract
Anticipatory Learning Classifier Systems (ALCS) provide an interpretable symbolic approach to reinforcement learning, but their practical use is often limited by the cost of maintaining evolving rule populations. This paper presents a unified ACS2 framework for comparing five execution regimes: a symbolic baseline, single-process CPU execution, multiprocessing CPU execution, sequential independently seeded tensorized GPU execution, and the same PyTorch tensor backend executed on the host CPU. The contribution is primarily systems- and methodology-oriented rather than algorithmic: the framework enables controlled comparison of runtime, exploit-phase behavior, and maintained population size across distinct ACS2 implementations. The tensorized backend reformulates nearly the full ACS2 learning loop in dense tensor form, including matching, anticipatory updates, offspring handling, and fixed-capacity population management. Benchmarking over the full ACS2 maze suite shows that the multiprocessing CPU backend provides the best overall wall-clock runtime, whereas the single-process CPU backend yields the best average per-experiment runtime. The tensorized modes achieve lower exploit-step averages, but they remain substantially more expensive in runtime terms and must be interpreted cautiously because backend realization also changes population-management semantics. The resulting framework therefore contributes a reproducible basis for studying runtime-population trade-offs and semantic divergence across ACS2 execution strategies.
Hidden Semi-Markov Models (HSMMs) are fundamental probabilistic models widely adopted across diverse domains, from computational biology to finance and signal processing. The Viterbi algorithm decodes the most likely state sequence given an HSMM and can be applied iteratively for ab initio model learning. However, existing Viterbi implementations remain sequential, and GPU-accelerated solutions are entirely absent, making HSMM decoding impractical for large-scale workloads. We present a tensor-based formulation of the Viterbi algorithm for HSMMs, restructuring the inner loops into tensor operations that naturally map onto SIMD units and massively parallel architectures. Building on this formulation, we provide optimized implementations spanning single- and multi-core CPUs, and, for the first time, GPU. Experimental evaluation demonstrates speedups of up to 14x on a single core, over 200x with multi-core, and over 570x on GPU over the state-of-the-art sequential baseline, establishing a new performance baseline for large-scale HSMM decoding.
Lorenzo Piarulli, E. Belli, D. De Sensi· 0 citations
We introduce AMDKernelVault, an open HIP and Triton kernel corpus and training framework for recent AMD CDNA GPUs. Existing LLM-based kernel agents are largely CUDA/NVIDIA-centric and often depend on repeated frontier-LLM calls for generation, reflection, and optimization. To address this gap, we develop HIPKernelGen and TritonKernelGen, agent-driven pipelines that transform PyTorch references into HIP or Triton kernels, compile and validate candidates under ROCm, and latency-profile them on AMD hardware. The corpus contains 62,153 execution-verified HIP kernel samples, 2,377 production-grounded ROCm Libraries QA entries, and 39,893 Triton kernels. We further train Qwen3-8B with supervised fine-tuning and execution-aware reinforcement learning as a demonstration of the corpus's utility. Under fixed evaluation budgets, it achieves the highest correctness among the compared models on PyTorch-to-HIP (34.0% Pass@1), TritonBench-G (33.2% Corr@3), and ROCmBench (41.94% Corr@3), but does not uniformly lead compilation or speed metrics. The corpus and documentation are available at https://huggingface.co/datasets/amd/AIG-Datasets, and the associated training and kernel-generation code is available at https://github.com/AMD-AGI/hip_kernel_llm_lab.
Ji Liu, S. Majumder, Yi-Qing Huang et al.· 0 citations
ES-HyperNEAT evolves substrate topology through adaptive quadtree subdivision; to our knowledge, no implementation with full population-level GPU parallelization exists. We present JAX-ESHN, a JAX-based implementation targeting GPU parallelization with batched CPPN queries, and benchmark it against the CPU-based PUREPLES Baseline across five tasks: XOR, Parity-3, circle classification, sine regression, and CartPole. The core limitation is structural: each CPPN discovers a unique set of substrate positions, preventing population-level vectorization via vmap. On XOR, the CPU Baseline's runtime scales exponentially with depth while JAX-ESHN's construction cost on GPU (compilation plus first-generation evaluation) plateaus at deep substrates, so JAX-ESHN solves reliably where the Baseline rarely succeeds, with lower runtime variance. A CPU-vs-CPU multi-benchmark control reproduces the same scaling divergence across Boolean, continuous, and control task types, confirming it is a property of the substrate-discovery implementation, not of GPU hardware. An alternative data structure (Hierarchical Spatial Hash Grid) fails not because it precomputes positions but because it applies the variance test independently per position, discarding the quadtree's parent-gated filtering and with it the adaptive sparsity essential to ES-HyperNEAT. These findings define the structural constraints any substrate-discovery method must satisfy to scale coordinate-based neuroevolution; the companion EMR-HyperNEAT reformulation, which replaces adaptive subdivision with eager evaluation of a static multi-resolution grid, satisfies them and resolves the bottleneck this paper characterizes.
Romain Claret, Michael O'Neill, Paul Cotofrei et al.· 0 citations
As the complexity of High Performance Computing (HPC) ecosys- tems continually increases, achieving optimal performance becomes a challenge. Traditional performance autotuning techniques pro- vide promising means to navigate this complexity, these techniques remain computationally intensive and require many evaluations to find optimal configurations. This work proposes an autotuning framework that designs a machine learning-based ensemble LLVM Intermediate Representa- tion (IR) ranker, Neural Configuration Scorer (NCS). NCS ranks the performance of IRs sampled by a transfer-learning-based autotuner, improving the efficiency of the tuning process by reducing tuning overheads and circumventing subpar evaluations. By leveraging knowledge from related tasks, we are able to effectively exploit the transfer relationship to access high-performing configurations in fewer samples than traditional techniques that rely upon itera- tive refinement. Our framework can achieve similar performance improvements as state-of-the-art autotuning techniques with up to 61.67% fewer evaluations, averaging 27.85% fewer evaluations across various HPC benchmarks.
Md Arafat Hossain, Thomas Randall, Akashnil Dutta et al.· 0 citations
The deployment of Deep Learning models on heterogeneous hardware necessitates optimized tensor programs to utilize computational resources. While auto-tuning frameworks like Ansor employ evolutionary search strategies, they suffer from limitations, including slow convergence, memory consumption, and a tendency to stagnate in local optima within high-dimensional, non-convex search spaces. To address these challenges, this paper proposes CoDSA (Coordinate Descent with Dynamic Simulated Annealing), a hybrid auto-tuning framework that integrates an enhanced Droplet Search algorithm into the Ansor ecosystem. We introduce three improvements to the droplet coordinate descent strategy: 1) a Dynamic Simulated Annealing mechanism to escape local optima; 2) an Adaptive Step-Size Control modulated by an exploration factor to balance global traversal and local refinement; and 3) a Diversity Control mechanism utilizing cosine similarity to enforce orthogonal exploration. Experiments on NVIDIA GPUs using Vision Transformer, DeiT, and Swin Transformer models demonstrate that CoDSA outperforms the Ansor framework. Specifically, for the ViTBase model, our method reduces search time by 37.2% and memory usage by 53.1%, while improving inference latency by up to 26.5% on complex architectures like Swin-Small. This work bridges the gap between the global exploration capability of evolutionary methods and the rapid exploitation efficiency of coordinate descent.
Rui-Ting Sun, Honglu He, Guanwen Zhang et al.· Information Technology and C...· 0 citations
The rapid rise of AI-oriented accelerators has reshaped compute systems around low-precision tensor engines, raising a practical question for the HPC community: under what conditions can such hardware support scientific workloads that demand numerical robustness, irregular memory access, and scalability? Using the Ascend 910 NPU series as a representative tensor-centric platform, we characterize precision, execution, and memory-hierarchy bottlenecks that hinder the direct deployment of scientific codes. We then develop and evaluate workload-specific mappings across five application studies -- HPL-MxP, LRSVD, SGEMM-cube, PQSim, and SMC-X -- combining heterogeneous execution, mixed-precision numerical formulations, precision emulation, hierarchical memory orchestration, and communication--computation overlap. These studies show that AI-native NPUs can achieve numerical robustness, competitive performance, and satisfactory scalability when numerical formulation, execution placement, and data movement are addressed in a coordinated manner. Our results provide a state-of-the-practice case study of how scientific workloads can be adapted to tensor-centric architectures, while distinguishing transferable optimization principles from Ascend-specific implementation details.
Weicheng Xue, Kai Yang, Yongxiang Liu et al.· arXiv.org· 0 citations
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