DPIO: A Unified I/O Architecture for Heterogeneous CPU and DPU NVMeoF

Spillway: Orchestrating DPU and Host into a Unified vSwitching Fabric

Spillway introduces a DPU-host hybrid data plane that repurposes idle host CPU resources to process spillover traffic when the DPU becomes the bottleneck, and decouples virtual switching capacity from static DPU hardware limits.

Single-Core Hotspots on Your VNF? Break Them Up!

ParaFlowO is proposed, an architecture that Parallelizes processing elephant Flows across multiple CPU cores while preserving in-Order delivery and integrates a lightweight reordering mechanism to preserve packet order and controls parallelism to mitigate contention on shared state.

A Unified Bandwidth Orchestration Framework for Hierarchical Data Storage Systems

HARMONI: Heterogeneity-Aware I/O Scheduling for Mixed Workloads in SSD-Based HPC Systems

Modern HPC systems increasingly rely on tiered storage architectures with SSDs serving as a critical performance tier. However, the inherent asynchronous I/O characteristics of SSDs, including read/write bandwidth asymmetry and interference, pose significant challenges for traditional I/O schedulers. These challenges are exacerbated by the convergence of bursty HPC write workloads (e.g., checkpointing) and sustained AI read workloads (e.g., data streaming) on shared SSD infrastructure. Existing schedulers fail to adequately address these combined workloads, leading to suboptimal resource utilization. This paper introduces HARMONI, a heterogeneity-aware reinforcement learning scheduler for mixed I/O in HPC storage systems. HARMONI leverages a graph neural network (GNN) to encode task-SSD dependencies and a hybrid interference predictor to adapt to hardware and I/O variations. Experimental results across diverse HPC and AI workloads demonstrate that HARMONI significantly reduces average makespan by up to 90% compared to state-of-the-art schedulers, effectively bridging the gap between evolving storage hardware and the dynamic I/O demands of modern HPC systems.

Achieving High-Performance Erasure Code Repair Through DPU Offloading

Erasure coding provides efficient fault tolerance for large-scale distributed storage systems. However, its data repair process is well-known to be resource-intensive. We find that conventional host-centric, TCP-based repair architectures suffer from severe resource contention. Even in high-bandwidth networks, such interference slows repair operations and degrades service quality. To address this limitation, we propose DPUEC, a novel architecture that fully offloads the entire repair process to a Data Processing Unit (DPU). DPUEC leverages Remote Direct Memory Access (RDMA) to enable kernel-bypass data transfers and utilizes the onboard multi-core processors of DPU for highly parallel decoding. This design establishes a physically isolated data plane for repair traffic, completely bypassing host resources. Our prototype evaluation shows that DPUEC improves repair throughput by 133% - 181% over the state-of-the-art approach across different workloads. More importantly, DPUEC delivers true performance isolation. It eliminates any interference with foreground applications and reduces host CPU utilization on the recovery node to nearly zero.

Toward Disaggregated Analytical Database Systems in the AI Hardware Era

The AI hardware boom has driven modern data centers toward HPC-style architectures centered on GPU clusters, RDMA-capable networks, and high-throughput NVMe storage. While designed primarily for training and inference, this infrastructure also creates new opportunities for designing the next generation of scalable database systems for analytical workloads on top of such data centers. In particular, the combination of GPU-centric computation, fast networking, and fast storage enables disaggregated architectures that extend beyond single-node, GPU-memory-resident execution. This paper discusses the challenges and design considerations of analytical query processing on such disaggregated GPU-centric systems. We examine how modern networks and storage enable distributed execution and out-of-memory processing, and how their interaction shapes end-to-end performance. Our recent results show that naïve use of existing I/O abstractions can underutilize both compute and I/O bandwidth due to insufficient overlap between computation and data movement. We therefore identify effective I/O-computation overlap as a key requirement for fully exploiting the AI data center stack, and outline future research directions for next-generation analytical database architectures.