A 65-nm Compute-in-PUF Engine for On-Chip Learnable Anomaly Detection Using 2T--2T PUF Arrays

Abstract

With the rising threats of side channel attacks and complexities of both on-chip and ambient environment, it is demanding to incorporate on-chip learnability into side channel attacks anomaly detection. This will enable offline-trained models to adapt to the new power profiles of emerging side channel attacks schemes, workloads, and varying environments. Existing side channel attacks detection techniques often fall short in in-situ learning or pose excessive on-chip integration challenges due to resource and data demands. This paper presents a novel neuromorphic “compute-in-Physical-Unclonable-Function” architecture, validated in 65 nm CMOS, designed for side channel attacks detection with on-chip learning capability and optimized area, energy and data overheads. We harness the physical unclonable function based key generator as a hyperdimensional encoder, enabling few-shot learning capabilities. The test chip achieves a detection accuracy of 97.2% and demonstrates true adaptability, restoring accuracy by up to 52% within a 5 ms after workload change. By unifying the security primitive and the compute engine, our design is achieve $7.5\times $ transistors reduction compared with an equivalent SRAM-based system while only imposing a 23.4% area overhead for the entire on-chip learning module. This work demonstrates a practical, silicon-proven solution that offers scalable, efficient and, adaptive security.