Scalable Verification for Dot-Product Architectures Using Symbolic Computer Algebra

Polynomial Formal Verification of Structurally Simple Multipliers

Formal verification of integer multipliers remains a challenging problem in electronic design automation, as logic-based approaches such as Satisfiability Solvers (SAT) and Binary Decision Diagrams (BDDs) often scale poorly on such circuitry. In recent times, Polynomial Formal Verification (PFV) has been investigated f...

Randomized Transduction for High-Effort Logic Synthesis

A novel variation of high-effort logic synthesis called transduction is presented, which performs transformation and reduction using don’t-cares to restructure the circuit.

Benchmarking Large Language Models on HDL Generation of Cryptographic Primitives

While large language models (LLMs) are now competent at generating software in languages such as C and Python, their use to generate hardware description language (HDL) for digital circuits is less explored. In this paper we evaluate seven LLMs on the generation of Verilog for 25 crypto-graphic primitive tasks drawn fr...

Machine Learning Approach to ATPG in VLSI Circuits Using Random Forest Regressor

As the need for highly advanced chip technology and high-performance computing grows, semiconductor technology must develop rapidly. Also, as VLSI circuits become more complex, it is more difficult and time-consuming to test circuits using traditional test methods. Hence, Chip design, verification, and testing become e...

Multiplier Optimization by Exploring Logical Correlations Among Partial Products

CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs

CircuitGate is proposed, a function-aware AIG representation learning framework that advances from gate-level semantics to circuit-level functional modeling, and achieves the best equivalent-gate identification performance, demonstrating strong cross-dataset generalization.