FPGA Implementation and Comparative Hardware Analysis of FPLP Trivium and Prince

Abstract

A lightweight cryptographic hardware is crucial in cases where computing capabilities, silicon area and power requirement are limited. In this paper, the design of FPGA-based FPLP architecture for Trivium stream cipher algorithm is provided with analysis of the hardware parameters of FPLP architecture in Spartan-7, Artix-7 and Kintex-7 devices. The proposed design is implemented by Verilog HDL language and synthesis process has been done using Xilinx Vivado Design Suite 2024.2. Resource utilization, maximum frequency, throughput, throughput-per-area and power consumption are considered as evaluation parameters. The designed architecture utilizes 149 LUTs in all three target devices, while the utilization rate of slices varies from 69 to 73 slices. Maximum operating frequency is achieved up to 663.1 MHz in Kintex-7 device, while the throughput equals 1326.2 Mbps and throughput per slice is equal to 18.16 Mbps/slice. Power consumption values obtained through experiments for Spartan-7, Artix-7, and Kintex-7 are 106 mW, 140 mW, and 122 mW respectively. Further, a comparison between the design architecture and the existing FPGA architectures that are used to implement the PRINCE light weight block cipher is done. Since Trivium and PRINCE are two different cryptography algorithms whose FPGA implementation is done on different platforms, this comparison is done to make a comparison of the efficiency of hardware and not the performance of the algorithm.