BHARAT-TPM: Design and ASIC Implementation of an SPI Based AXI Enabled RNG Accelerator

Abstract

Public Key Infrastructure (PKI) systems depend on hardware RNGs for key pair generation, certificate signing, and secure session establishment, making high quality entropy a critical requirement in TPM based secure platforms. Trusted Platform Modules (TPMs) serve as hardware roots of trust in secure SoC environments, supporting cryptographic key generation, digital signatures, secure authentication, and high quality random number generation essential for PKI operations. However, standalone pre-integration validation of AXI based entropy generation accelerators through a serial interface remains unaddressed in existing literature. This paper presents a deterministic and reusable hardware validation framework for AXI based cryptographic IP cores, realized as a structured, packet based SPI to AXI validation architecture, introducing a reusable SPI driven validation methodology for pre-integration verification of AXI based cryptographic accelerators. The proposed architecture employs dual clock domain synchronization and FIFO based buffering to ensure reliable data transfer between the SPI interface and the AXI enabled RNG accelerator, supporting entropy generation with runtime health monitoring compliant with NIST SP 800-90B guidelines, ensuring entropy quality required for PKI operations. The design is implemented in Verilog HDL and validated on the Xilinx Virtex UltraScale VCU108 FPGA achieving 250 MHz with 21847 LUTs and 30069 flip-flops, serving as a hardware verification platform within the RISC-V based BHARAT-TPM.