2026· IEEE Transactions on Information Forensics and Security· Vol 21, pp. 7332-7345· 0 citations· 52 references
Computer Science
Abstract
Programmable Logic Controllers (PLCs) are core components of Industrial Control System (ICS), and their security is essential for the reliable operation of critical infrastructure. However, PLCs are vulnerable to RunStage Attacks, which are runtime attacks that occur when the PLC is in the “Run” mode executing control logic. In the class of RunStage Attacks considered in this work, adversaries corrupt memory and hijack control flow to manipulate control logic. Due to the limited resources and stringent real-time requirements of PLCs, existing control flow defense schemes still suffer from shortcomings in resource usage and real-time performance. To address these challenges, we propose TLCFI-PLC, a trampoline-based lightweight control flow integrity scheme for defending against RunStage control flow hijacking attacks. The scheme consists of two phases: offline analysis and online monitoring. In the offline analysis phase, TLCFI-PLC parses the PLC binary control logic and employs trampoline-based instrumentation to constrain control flow execution, avoiding large-scale rewriting that could alter the memory layout or program size. It then extracts legitimate target addresses and execution paths to construct a control flow integrity baseline. In the online detection phase, the instrumented PLC records runtime control flow information to shared memory, where an asynchronous checker monitors execution paths and detects hijacking attempts. We implemented a prototype on a WAGO PLC running the CodeSys runtime environment. Experiments show that, among the 248 selected case studies, the sizes of the processed files ranged from 44 KB to 552 KB, and the instrumentation time was generally less than 5 seconds. Two supplementary sets of 10 binaries were evaluated: a scenario-oriented set for binary-size overhead, averaging below 1%, and a randomly selected set for scan-cycle time, which remained within acceptable limits. These results further confirm the robustness of the proposed scheme.
The efficacy of the lightweight security-aware RISC architecture as a feasible compromise between security, performance, and hardware expense in today’s embedded systems is indicated.
K. Kannaiah, S. Jogi, B. N. K. Reddy· Chips· 0 citations
PLCBENCH is presented, to the authors' knowledge, the first real-PLC hardware-in-the-loop (HIL) framework for characterizing this cyber-to-physical capability and its boundaries and it combines vendor-native interaction, commercial PLC execution, closed-loop reduced-order process simulation, and independent outcome ver...
Yitian Zhou, Jing-Yu Zheng, Qi-Liang Jiang et al.· 0 citations
This study focuses on developing a Cryptographic Message Authentication Code (CMAC) Intrusion Detection System (IDS) implementation for CAN bus communication using existing ECUs.
Spencer Beer, Jake Jepson, A. Nogin et al.· SAE technical paper series· 0 citations
An architectural analysis of automotive HSMs is presented and examines their role in establishing secure boot and hardware roots of trust and emerging challenges such as cryptographic agility and post-quantum readiness that are likely to shape the next generation of automotive HSM architectures are discussed.
benchmarking proves that hybrid systems are computationally trivial relative to classical systems, thus, the suggested defence-in-depth design bridges the significant gap between practical post-quantum security and industrial application.
H. A, Shanmugapriya K, L. Jabasheela et al.· International journal of com...· 0 citations
A Field-Programmable Gate Array-based state evolution architecture that provides hardware-enforced one-way state updates, runtime tamper detection, and fail-secure containment and uses Ascon-Hash256, a National Institute of Standards and Technology standardized cryptographic algorithm for constrained devices.