A 12-bit Hybrid SAR-Time-Domain ADC for New Space Systems

Abstract

This paper presents a 12-bit hybrid analog-to-digital converter (ADC) for harsh-environment and Low Earth Orbit (LEO) applications. The architecture partitions the conversion into a 4-bit coarse successive approximation register (SAR) stage and an 8-bit fine time-domain stage. By confining the binary-weighted capacitor array to only four bits and delegating the remaining resolution to a programmable multi-ramp switched-capacitor stage, the design significantly reduces capacitive complexity while preserving high resolution. This coarse-fine segmentation is particularly advantageous for radiation-prone environments, as it limits capacitor-array size, improves mismatch tolerance, and facilitates implementation in open-source design flows such as OpenFASOC. Behavioral simulations and design-space exploration demonstrate that the proposed partition achieves the target 12-bit resolution with compact implementation, bounded static nonlinearity, and substantial conversion-time advantage over conventional multi-ramp architectures, making it a promising solution for New Space SoCs.