Trade-Off Study of Multi-Bypass Bin Designs for VVC/H. 266 Binary Arithmetic Encoding

Abstract

Video traffic dominates modern network usage, driving the need for efficient compression solutions that balance high throughput with low power and area consumption. The Versatile Video Coding (VVC/H.266) standard addresses this challenge using Context-Adaptive Binary Arithmetic Coding (CABAC) as its entropy coding engine. However, the inherently sequential nature of CABAC, particularly in the Binary Arithmetic Encoder (BAE), limits throughput in hardware implementations. This work explores the use of Multiple Bypass Bin Schemes (MBBS) to enable parallel processing of bypass bins, a class of CABAC inputs with simplified probability modeling. While increasing throughput with a hardware accelerator is the optimal solution, the need for smaller area and lower power consumption is also crucial. Therefore, three hardware architectures are designed to support different degrees of parallelism and synthesized to evaluate their impact on throughput, area, and power. The results show that increasing parallelism improves throughput, but with diminishing returns and significant hardware overhead at higher levels. In particular, the two-bypassbin architecture achieves the most balanced trade-off, providing notable throughput gains with moderate area and power cost.