An OpenSHMEM Auxiliary Specification for GPU-Aware Communication is proposed, designed as a lightweight, backward-compatible extension to OpenSHMEM 1.x, to demonstrate that GPU-aware OpenSHMEM semantics can be specified and implemented across GPUs from multiple vendors, providing a practical and rapidly implementable step toward unification under a vendor-neutral specification.
Abstract
Leadership-class HPC systems are now accelerator-centric, with GPUs providing most floating-point throughput and memory bandwidth. As next-generation systems increasingly integrate accelerators through high-speed memory fabrics and system interconnects, exposing larger tightly coupled device domains, \ac{PGAS} models such as OpenSHMEM provide a natural abstraction for expressing fine-grained remote memory operations across these devices. While OpenSHMEM 1.x offers a lean PGAS model for irregular communication, atomics, fine-grained synchronization, and collectives, its memory model lacks portable semantics for accelerator architectures. As a result, existing GPU-enabled OpenSHMEM implementations differ in memory management, capability discovery, and operation semantics, limiting portability and ecosystem cohesion. This risks fracturing the community that OpenSHMEM was originally created to unify. This paper proposes an OpenSHMEM Auxiliary Specification for GPU-Aware Communication, designed as a lightweight, backward-compatible extension to OpenSHMEM 1.x. The auxiliary specification introduces a minimal memory model extension via a GPU-scoped memory space abstraction, along with capability queries and well-defined semantics for using \acs{GPU}-attached buffers in RMA, atomic, synchronization, and collective operations. This is initially conceived through the lens of a host-initiated interface, although it provides a general set of semantics that also allow for optional device-initiated support. A central goal of this effort is to demonstrate that GPU-aware OpenSHMEM semantics can be specified and implemented across GPUs from multiple vendors, providing a practical and rapidly implementable step toward unification under a vendor-neutral specification while informing the design of future OpenSHMEM specifications.
OpenMP 5.0 introduced the Unified Shared Memory (USM) feature through the requires directive. The feature simplifies the adoption of the OpenMP programming model by providing a unique and common address space between the accelerators and the host and allowing the access (dereference) of the same memory address on different devices, thus avoiding the burden of explicit data transfers to maintain the consistency between the address spaces. Hence, the feature eases quick prototyping and porting of applications to OpenMP with accelerators. In this paper, we introduce the Intel implementation for USM. We briefly discuss its implementation in the software stack (OS kernel, compiler, and runtime), then assess its adoption complexity in existing HPC applications using OpenMP for accelerators, and, finally, evaluate the performance of these applications when adopting USM on an Intel Battlemage GPU. USM is not expected to grant performance uplifts to already optimized applications with explicit, granular data-motion control and our results show an overhead with a geometric mean below 1.2x (1.03x seems achievable with further optimizations). Yet, in this paper we show there exist applications that benefit from this feature, making it attractive even for already ported applications.
Harald Servat, François Dugast, A. Duran et al.· arXiv.org· 1 citation
This paper describes DeepSig's CUDA-based acceleration backend for the OCUDU physical layer and O-RAN fronthaul path, integrated through acceleration interfaces that are largely independent of the underlying acceleration mechanism. The design accelerates PDSCH, PUSCH, SRS, PRACH, split-8 lower-PHY transforms, and O-RAN fronthaul (O-FH) IQ compression/decompression while preserving existing factories, resource-grid interfaces, PRACH-buffer interfaces, and channel processors. CUDA-visible grids, device-side softbit buffers, stream events, pinned staging buffers, and managed-memory policies keep data resident on the accelerator when the platform and radio split permit it. On an NVIDIA DGX Spark platform with a GB10 GPU and ARM CPU host, representative measurements with CPU baselines pinned to high-capacity cores show up to 10.3x PUSCH speedup, 2.7x PDSCH speedup, 19.7x split-8 low-PHY RX speedup with slot-shaped batching and scattered mapped zero-copy, 91.4x O-FH BFP12 decompression speedup, and 28.8x PRACH detector speedup against the production CPU path, with CPU and GPU 10% BLER thresholds agreeing to within 0.064 dB in the tested PUSCH sweeps. The same resident pipeline provides an execution substrate for AI-RAN, allowing machine-learned channel estimation, neural receivers, and AI-native air-interface research to run beside standards-compliant baseband kernels.
M. Pennybacker, Wanze Liu, A. Kharchenko et al.· 2 citations
Moving from quantum research and development to production-grade, fault-tolerant quantum workload execution remains one of the most significant challenges facing quantum platform builders. While Python frameworks have enabled an easy entry point for quantum algorithm design, the low-latency requirements for real-time quantum error correction (QEC) demand performance that traditional interpreted environments cannot provide. FPGAs and ASICs play a central role at these layers, but their specialized programming models make development rigid and time-consuming. CPUs, GPUs, and other accelerators introduce a different challenge: as infrastructure becomes increasingly heterogeneous, programming across different devices and their associated abstractions becomes more complex. Allowing researchers to write workloads in high-level languages that map to low-latency execution across diverse distributed target platforms will enable the development of key infrastructure for utility-scale quantum systems. For this, we introduce $\textit{Backline}$, a heterogeneous compilation and runtime framework built within PennyLane and Catalyst. Backline allows us to design and build quantum-classical workloads for high-performance and low-latency devices, with compilation directly from a Python interface through MLIR. We demonstrate the compilation and execution of several quantum workloads with low-latency data movement across a mix of CPUs, GPUs, and FPGAs, for both local and distributed remote hardware targets, all from a vendor-agnostic Python frontend. With an AMD VPK120 FPGA board as the controller, issuing each round from its hardware-handshake engine, we measured median steady-state round-trip latencies over RoCE v2 of $2.305~\mu$s to an AMD Ryzen Threadripper PRO CPU and $4.5~\mu$s to an AMD Instinct MI210 GPU across $10^6-1$ rounds per path, demonstrating microsecond-scale synchronous co-processing.
Joseph K. L. Lee, M. Malekmohammadi, Hong-Sheng Zheng et al.· 0 citations
(English) The continuous evolution of multiprocessor and heterogeneous computing systems has led to a dramatic increase in architectural complexity, providing higher throughput and energy efficiency. Such advancements have been boosted by the technological development of chiplet-based architectures, which enable further scaling of transistor count. The downside is that long-standing challenges, such as synchronization and data sharing, continue to worsen. At the heart of synchronization lie atomic memory operations (AMOs), hardware-supported read–modify–write primitives that ensure correctness and coordination among concurrent threads. However, as systems scale toward hundreds of cores, integrate heterogeneous compute engines, and adopt chiplet-based packaging, traditional AMO implementations face serious scalability and latency bottlenecks.
This thesis presents a set of architectural and microarchitectural innovations to enhance the efficiency, flexibility, and adaptability of AMOs across future coherent manycore and heterogeneous systems. The thesis addresses three fundamental challenges. First, existing instruction set architectures (ISAs) lack direct support for floating-point atomic operations, forcing programmers to emulate them using compare-and-swap (CAS) loops that degrade performance and increase contention. Second, current AMO implementations employ static policies that determine their execution point, either near the core (in the L1 cache) or far in the memory hierarchy (e.g., at the last-level cache or directory), without adapting to application behavior. Third, far AMOs are typically centralized, meaning that all updates to a memory location are serialized through a single point, creating contention and coherence traffic that limit scalability in chiplet-based and distributed cache architectures.
The first contribution extends the Arm architecture with Floating-Point Atomic Memory Operations (FAMOs). FAMOs enable hardware-level atomic operations on floating-point data, removing the need for inefficient CAS-based software constructs. Extensive evaluation across high-performance computing (HPC), graph analytics, and machine learning workloads demonstrates that FAMOs achieve up to 1.58x performance improvement and reduce synchronization latency by over 30%.
The second contribution proposes DynAMO, a runtime mechanism that dynamically selects the optimal AMO execution placement based on data locality and reuse patterns. By analyzing temporal reuse and coherence activity, DynAMO predicts whether performing an AMO locally or remotely will minimize latency and data movement. Experimental results show that DynAMO outperforms the best static policy by an average of 1.09x across all workloads, and up to 1.31x in AMO-intensive applications, improving both performance and energy efficiency. The third contribution introduces a new class of delegated and migrating AMOs that eliminate the limitations of centralized far AMOs. Additionally, we propose Delegato, an AMO predictor at the directory level. Delegato allows the coherence directory to delegate the execution of an AMO to the current data owner or migrate the atomic operation to a more suitable cache level, effectively distributing synchronization across the memory hierarchy. Combined with predictive mechanisms that trace locality and reuse, Delegato achieves up to 1.13x speed-up over state-of-the-art approaches while reducing interconnect traffic and cache invalidations in chiplet-based systems.
(Català) L'evolució contínua dels sistemes de computació multiprocessador i heterogènia ha provocat un augment dràstic en la complexitat arquitectònica, proporcionant un rendiment i una eficiència energètica més alts. Aquests avenços han estat impulsats pel desenvolupament tecnològic de les arquitectures basades en chiplets, que permeten una escalabilitat més gran en el nombre de transistors per reticle. L'inconvenient és que els problemes fonamentals dels multinúclis, com la sincronització i l'intercanvi de dades, continuen empitjorant. Al cor de la sincronització es troben les operacions atòmiques de memòria (AMO), primitives de lectura-modificació-escriptura suportades pel hardware que garanteixen l'execució correcta i la coordinació entre fils concurrents. No obstant això, a mesura que els sistemes escalen cap a centenars de nuclis, integren unitats de còmput heterogènies i adopten empaquetaments basats en chiplets, les implementacions tradicionals d'AMO s'enfronten a colls de botella greus d'escalabilitat i de latència.
Aquesta tesi presenta un conjunt d'innovacions arquitectòniques i microarquitectòniques per millorar l'eficiència, la flexibilitat i l'adaptabilitat de les AMO en futurs sistemes coherents multinúcli i heterogenis. La tesi aborda tres desafiaments fonamentals. Primer, els conjunts d'instruccions (ISA) existents no tenen suport directe per a operacions atòmiques de coma flotant, obligant als programadors a emular-les mitjançant bucles de compare-and-swap (CAS) que degraden el rendiment i augmenten la contenció. Segon, les implementacions actuals d'AMO fan servir polítiques estàtiques que determinen el lloc d'execució, ja sigui prop del nucli (a la memòria cache L1) o lluny en la jerarquia de memòria (p. ex., a la memòria cache d'últim nivell o al directori), sense adaptar-se al comportament de l'aplicació. Tercer, les AMO remotes solen estar centralitzades, cosa que significa que totes les actualitzacions es serialitzen en un únic punt, generant contenció i tràfic de coherència que limiten l'escalabilitat en arquitectures de memòria cache distribuïdes i basades en chiplets.
La primera contribució estén l'arquitectura Arm amb Operacions Atòmiques de Memòria de Punt Flotant (FAMOs). Les FAMOs permeten operacions atòmiques en hardware sobre dades de coma flotant, eliminant la necessitat de construccions de software ineficients basades en CAS. Una avaluació exhaustiva en càrregues de treball de computació d'alt rendiment (HPC), anàlisi de gràfics i aprenentatge automàtic demostra que les FAMOs assoleixen una millora de rendiment de fins a 1.58x i redueixen la latència de sincronització en més d'un 30%.
La segona contribució proposa DynAMO, un mecanisme dinàmic en temps d'execució que selecciona dinàmicament la ubicació òptima d'execució d'AMO basant-se en la localitat de les dades i els patrons de reutilització.
En analitzar la reutilització temporal i l'activitat de coherència, DynAMO prediu si realitzar una AMO local o remota minimitzarà la latència i el moviment de dades. Els resultats experimentals mostren que DynAMO supera la millor política estàtica en una mitjana de 1.09x en totes les càrregues de treball, i fins a 1.31x en aplicacions intensives en AMO, millorant tant el rendiment com l'eficiència energètica.
La tercera contribució introdueix dues noves classes d'AMOs, delegades i migratòries, que eliminen les limitacions de les AMO remotes centralitzades. Addicionalment, es proposa Delegato, un predictor de localització d'AMOs en el nivell del directori. Delegato permet que el directori de coherència delegui l'execució d'una AMO al propietari actual de les dades o migri l'operació atòmica a un nivell de memòria cache més adequat, distribuint eficaçment la sincronització a través de la jerarquia de memòria. Delegato combinat amb mecanismes predictius que rastregen la localitat i la reutilització, Delegato assoleix una acceleració de fins a 1.13× sobre l'estat de l'art
(Español) La evolución continua de los sistemas de computación multiprocesador y heterogénea ha provocado un aumento drástico en la complejidad arquitectónica, proporcionando mayor rendimiento y eficiencia energética. Tales avances han sido impulsados por el desarrollo tecnológico de las arquitecturas basadas en chiplets, que permiten una mayor escalabilidad en el número de transistores por retículo. La desventaja es que los problemas fundamentales de los multicores, como la sincronización y el intercambio de datos, continúan empeorando. En el núcleo de la sincronización se encuentran las operaciones atómicas de memoria (AMO), primitivas de lectura-modificación-escritura soportadas por el hardware, que garantizan la correcta ejecución y la coordinación entre hilos concurrentes. Sin embargo, a medida que los sistemas escalan hacia cientos de núcleos, integran unidades de cómputo heterogéneas y adoptan empaquetados basados en chiplets, las implementaciones tradicionales de AMO enfrentan serios cuellos de botella de escalabilidad y de latencia.
Esta tesis presenta un conjunto de innovaciones arquitectónicas y microarquitectónicas para mejorar la eficiencia, la flexibilidad y la adaptabilidad de las AMO en futuros sistemas coherentes multinúcleo y heterogéneos.
La tesis aborda tres desafíos fundamentales. Primero, los conjuntos de instrucciones (ISA) existentes carecen de soporte directo para operaciones atómicas de coma flotante, obligando a los programadores a emularlas mediante bucles de compare-and-swap (CAS) que degradan el rendimiento y aumentan la contención. Segundo, las implementaciones actuales de AMO emplean políticas estáticas que determinan el lugar de ejecución, ya sea cerca del núcleo (en la cache L1) o lejos en la jerarquía de memoria (p. ej., en la cache de último nivel o en el directorio), sin adaptarse al comportamiento de la aplicación. Tercero, las AMO remotas suelen estar centralizadas, lo que significa que todas las actualizaciones a una ubicación de memoria se serializan en un único punto, generando contención y tráfico de coherencia que limitan la escalabilidad en arquitecturas de cache distribuidas y basadas en chiplets.
La primera contribución extiende la arquitectura Arm con Operaciones Atómicas de Memoria de Punto Flotante (FAMOs). Las FAMOs permiten operaciones atómicas en hardware sobre datos de coma flotante, eliminando la necesidad de construcciones de software ineficientes basadas en CAS. Una evaluación exhaustiva en cargas de trabajo de compu
In modern GPU-based non-unified heterogeneous systems, CPU-GPU communication happens via the PCI bus. Data transfers are affected by startup overhead, which underutilizes the PCI channel bandwidth for small transfers. Modern programming models, such as CUDA and OpenMP, treat each input argument to a compute kernel independently, leading to data movement segmentation and execution slowdowns. This work presents In-Copy Fusion (ICF), a runtime optimization of OpenMP’s accelerator model, implemented in LLVM, that gathers eligible map clauses into staging buffers, orchestrating an optimal transfer pipeline through fusion without modifying application or kernel code. The technique preserves OpenMP semantics with negligible overhead. We evaluate ICF across a range of representative HPC benchmarks and configurations, including varying argument counts, data sizes, and argument-size disparities, as well as real-world benchmarks. The results show that ICF improves effective host-to-device (H2D) bandwidth and reduces end-to-end time relative to the baseline runtime with per-argument transfers across platforms and workloads, achieving an up to 4.8 × speedup.
Dionisis-Odysseas Sotiropoulos, Sara Royuela Alcázar, Eduardo Quiñones et al.· Proceedings of the Internati...· 0 citations
Ghost is an OS-level GPU virtualization layer integrated directly into the open-source GPU driver, using a GPU container abstraction with cgroup -like APIs for compute and memory control and privileged hardware-level scheduling and preemption for dynamic compute resource management.
Unknown authors· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.
