Heterogeneous Computing Systems: A Review of Architectural Evolution and Design Methodologies

Abstract

Heterogeneous computing has emerged as an important architectural response to the slowdown of conventional semiconductor scaling, particularly in the post-Moore era. This review follows the shift from homogeneous multicore processors toward integrated platforms that place CPUs, GPUs, FPGAs, and domain-specific accelerators on the same die. The transition is closely related to two long-standing technology constraints, namely the slowing of Moore's Law and the breakdown of Dennard scaling, while Amdahl's Law still limits the speedup that can be obtained from parallel acceleration. From the system perspective, the review focuses on three recurring obstacles: the memory wall, cache coherence in shared-memory heterogeneous architectures, and on-chip communication supported by Network-on-Chip (NoC) designs. I also reviewed low-power VLSI approaches, especially clock gating and low-swing flip-flop designs, together with design methodologies such as SystemC-based high-level synthesis (HLS), the Catapult HLS flow, and latency-insensitive design. Based on these 24 research contributions, I organize the discussion into a multi-level technical framework for heterogeneous SoC design in AI and IoT applications.