This article investigates two lightweight field-programmable gate array (FPGA) implementations of an iterative NTT-based polynomial multiplication accelerator through non-pipelined and 4-stage pipelined architectures, showing that the non-pipelined architecture provides reduced hardware overhead and lower power consumption, whereas the pipelined architecture improves timing scalability and successfully operates at 280 MHz.
Abstract
Number Theoretic Transform (NTT)-based polynomial multiplication is a computationally intensive operation in lattice-based post-quantum cryptography (PQC) schemes such as CRYSTALS-Dilithium. Existing hardware accelerators optimize area and timing performance, without focusing on evaluating trade-offs among hardware utilization, execution latency, operating frequency, and power consumption. This article investigates such trade-offs through two lightweight field-programmable gate array (FPGA) implementations of an iterative NTT-based polynomial multiplication accelerator, namely non-pipelined and 4-stage pipelined architectures. Both implementations employ a single butterfly unit based on Cooley–Tukey and Gentleman–Sande configurations to compute the forward NTT (FNTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM). The 4-stage pipelined architecture employs pipeline registers in the modular multiplication and Barrett reduction datapaths to maximize the operating frequency. Both architectures are implemented on an Artix-7 FPGA and evaluated across operating frequencies ranging from 10 MHz to 280 MHz. The results show that the non-pipelined architecture provides reduced hardware overhead and lower power consumption, whereas the pipelined architecture improves timing scalability and successfully operates at 280 MHz. At the maximum operating frequency, the pipelined implementation utilizes 1115 slices and achieves execution times of 4.58 μs, 0.93μs, and 4.58μs for FNTT, CWM, and INTT computations, respectively, with an average power consumption of 133 mW. The Area–Time Product (ATP) and Energy–Delay Product (EDP) evaluations demonstrate that the pipelined architecture achieves improved overall efficiency within the proposed lightweight single-butterfly-based polynomial multiplication architecture at higher operating frequencies, obtaining an ATP of 7.74×103 Slice-μs and EDP of 1501.52 nJ-μs.
CRYSTALS-Kyber and CRYSTALS-Dilithium are representative lattice-based post-quantum cryptographic schemes, where number theoretic transform (NTT), inverse NTT (INTT), and point-wise multiplication (PWM) dominate polynomial arithmetic. Existing hardware accelerators are typically optimized for a single scheme or operation, resulting in limited scalability and redundant hardware resources. This paper presents a unified and scalable NTT/INTT/PWM architecture for both Kyber and Dilithium. A configurable two-dimensional processing-element (PE) array combined with an EVEN/ODD ping-pong memory organization enables conflict-free memory access and partial inter-stage pipelining. A unified K-RED-based modular multiplier supports either one Dilithium multiplication or two parallel Kyber multiplications using the same DSP resources, while PWM is mapped onto the existing PE array without requiring a separate complete PWM arithmetic array. Experimental results on a Xilinx Artix-7 FPGA show that the proposed modular multiplier reduces LUT utilization by 39.8% compared with the previous unified Kyber/Dilithium design. Under matched PE configurations, the proposed architecture achieves ATP reductions of up to 79.5% for Dilithium NTT/INTT and 73.9% for Kyber NTT/INTT, while the Kyber/Dilithium PWM mode achieves an ATP reduction of up to 78.3%. These results demonstrate that the proposed architecture provides an efficient, scalable, and highly reusable hardware solution for lattice-based post-quantum cryptographic accelerators.
Yuchen Wang, Xiaoke Wang, Chaoxing You et al.· Electronics· 0 citations
The iterative forward and inverse number theoretic transform (NTT) is a key component in lattice-based post-quantum cryptography (PQC), typically implemented using Cooley-Tukey and Gentleman-Sande butterfly units. Existing iterative NTT accelerators often rely on ping-pong memory schemes and large memory blocks tied to the cyclotomic ring, which limits overall efficiency. To overcome this, we propose a memory-parallelization strategy using four smaller n/4-sized memories for ring size n, preserving the total memory footprint of conventional designs. We also introduce a multiplication-free rescaling architecture for the inverse NTT. Building on these innovations, we perform a comprehensive hardware-based design space exploration of unified Cooley-Tukey and Gentleman-Sande butterfly units, evaluating both coarse- and fine-grained pipelining strategies. The resulting optimized butterfly unit forms the core of our proposed pipelined and memory-parallelized NTT accelerator,"PIP-NTT". It integrates two such units alongside the memory-parallelization scheme to boost computational throughput under tight area constraints. Experimental results on FPGA platforms show that PIP-NTT achieves 2.67x and 1.48x higher efficiency in average Area-Time Product compared to the most area-optimized and high-speed NTT accelerators in the literature. The design is scalable across butterfly radices and adaptable to other PQC schemes, making it a versatile solution for future cryptographic hardware
Malik Imran, A. Khalid, C. Rafferty et al.· arXiv.org· 0 citations
To satisfy the low-overhead and high-throughput requirements of embedded computing platforms executing cryptographic workloads, this study presents a high-performance RISC-V CPU IP core compatible with the standard RV32IM architecture. Instead of introducing dedicated cryptographic instructions, the proposed design enhances the execution efficiency of algorithms such as SM3 and SM4 through microarchitectural optimization of arithmetic units. A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput, while an enhanced radix-4 SRT divider incorporating leading-zero detection, result caching, and dynamic iteration control is proposed to reduce division latency. All modules are implemented in Verilog and integrated into a five-stage RISC-V pipeline. Functional verification is performed using a complete RVM instruction test suite, followed by FPGA-based performance evaluation. Experimental results demonstrate that the multiplier generates 64-bit results within a single clock cycle in 32-bit scenarios, reducing latency by more than 70% compared with conventional Wallace-tree implementations. The proposed architecture provides an efficient computing platform for secure embedded systems and offers implementation references for real-time signal processing, communication security, and electromagnetic information systems.
A systolic array-based accelerator prototype implemented on the Zynq-7000 SoC integrated directly into PyTorch, enabling dense linear algebra to be delegated to the FPGA chip while Cortex-A9 continues executing the software stack uninterrupted.
Omar Hernandez-Yañez, A. Juárez-Lora, J. Y. Montiel-Pérez et al.· Electronics· 0 citations
Arithmetic operations are fundamental to digital signal processing systems, where multipliers often decide overall performance constraints. They are key components of many high-performance systems such as Microprocessors, FIR Filters, Digital Signal Processors etc. The most common way of performing signed multiplication in digital circuits is by using booth multipliers, but the existing algorithm has a drain on power consumption since it never coerces operations to the full precision. In this paper, a novel 32-bit pipelined multiplier is designed aimed at achieving high throughput and low power consumption for VLSI applications. Modified Booth Encoding (MBE) with Radix-8 and Wallace tree reduction for partial products reduction and along with a CLA adder for partial products addition is used. Furthermore, a linear Pipelining technique with flipflops is implemented to minimize critical path delay. The Register Transfer level (RTL) model was implemented using Verilog and synthesized using Xilinx Vivado. Performance analysis demonstrates the reduction of delay by 23% and power consumption by 61%.
C.S. Chakradhar, M. Sreedhar· ITEGAM- Journal of Engineeri...· 0 citations
In the modern world, 128-bit binary arithmetic is essential for achieving high numerical accuracy but remains expensive to implement in processors. This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture. The SRMA-focused implementation not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards. Yet, today most of the processors are x86-64 CPU's which don't support floating point 128-bit calculations natively. On high performance processors, these generic methods trigger delayed pipelines and branch mispredictions, leading to longer clock cycles and increased energy. To unlock a processor's full potential, bridging the gap between slow software emulation and hardware support is a necessary task. The SRMA algorithm works on mantissa computations where it handles the branch-free arithmetics, where traditionally Generic algorithms use heavy branch-pipelining leading to unnecessary clock-cycles. This approach highlights the split-mantissa, an advanced approach where the mantissa of the scientific computations are split accordingly and then appended for minimal error. There is a bottleneck where software uses generic code that ignores the strengths of modern CPUs. Our ultimate goal is to run at speeds that make it practical for scientific computing at lower cost.
N. P, Thirumalaiswamy V., Harish Kumar S. et al.· International Journal of Com...· 0 citations
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