Domain-Specific Accelerators for Post-Quantum Cryptography

Abstract

The advent of large-scale quantum computing threatens the public-key infrastructure that secures modern digital communication, as Shor's algorithm renders the integer-factorization and discrete-logarithm problems underlying RSA and elliptic-curve cryptography tractable. In response, the National Institute of Standards and Technology (NIST) has standardized a first generation of quantum-resistant digital signature algorithms, namely the lattice-based CRYSTALS-Dilithium (ML-DSA, FIPS 204) and Falcon (FN-DSA) and the hash-based SPHINCS+ (SLH-DSA, FIPS 205). These schemes impose far higher computational and memory costs than their classical counterparts, which motivates domain-specific hardware accelerators able to meet the performance and energy budgets of practical systems. This survey reviews domain-specific accelerators for post-quantum signatures, giving equal attention to the three standardized schemes. For each, we examine the underlying construction, its parameter sets, and, above all, the implementation challenges that shape its hardware, from the rejection sampling of Dilithium to the floating-point Gaussian sampling of Falcon and the hashing-bound datapath of SPHINCS+. We compare reported FPGA and ASIC accelerators for every scheme, present a general-purpose accelerator template, and outline the emerging schemes and open challenges that will guide future hardware design. KeyWords: Post-Quantum Cryptography, Digital Signatures, Hardware Accelerators, FPGA, Falcon, Dilithium.