Algorithm-Hardware Co-Design for Efficient Vector Symbolic Autonomous World Modeling
TL;DR
This work introduces a state-of-the-art, out-of-order vector processor to natively accelerate VSA world modeling for autonomous systems with a power envelope of less than 130 mW, and unifies a structured, generalizable world model with hardware-efficient vector processing, which enables scalable and powerful autonomous systems.
Abstract
Autonomous systems operating in the open world require world models that are robust to uncertainty, capable of long-horizon reasoning, and able to generalize to novel scenarios. Vector Symbolic Architectures (VSA), particularly Fourier Holographic Reduced Representations (FHRR), learn robust, structured, and efficient interpretable world models for planning and control. In this work, we introduce a state-of-the-art, out-of-order vector processor to natively accelerate VSA world modeling for autonomous systems with a power envelope of less than 130 mW. We evaluate our hardware-software co-design, demonstrating a 4× reduction in energy per transition and a 2× improvement in roll-out throughput compared to GPU and CPU baselines while maintaining the model's accuracy. These gains are achieved by the vector processor's intrinsic support for element-wise unitary operations and parallel computation, which aligns perfectly with VSA algebra. By unifying a structured, generalizable world model with hardware-efficient vector processing, this work enables scalable and powerful autonomous systems.