Aug 2026· 2026 6th International Conference on Computer Science and Blockchain (CCSB)· pp. 259-263· 0 citations· 13 references
Abstract
Multi-protocol security platforms often integrate block, stream, and ARX ciphers on the same reconfigurable hardware. Instantiating independently optimized cipher cores preserves algorithm structure but duplicates linear bitwise logic and routing resources. This paper presents a reconfigurable multi-algorithm cryptographic IP core for AES, SM4, ZUC, and ChaCha based on operator-level sharing. The design keeps nonlinear and state-update logic inside each cipher core, while recurring XOR aggregation, shift, and rotation operations are implemented through a shared stateless operator layer under a unified top-level controller. Evaluation with the Verilog-to-Routing flow shows that, compared with an unshared baseline using the same integration framework, the proposed implementation reduces Configurable Logic Block utilization by 23.1% and total routing wirelength by 17.7%, with a 3.5% reduction in maximum operating frequency. The results demonstrate that operator-level sharing can reduce redundant hardware with limited timing impact.
PipSORE is introduced, a novel architectural optimization focused on area and power and the single- and multi-core PipSORE architectures are proposed and evaluated and utilize the outer-round pipelining technique.
M. M. Mahmoud, Sherif O. B. Farraj, Abeer Farouk Ali· Journal of Supercomputing· 0 citations
With the increasing demand for energy-efficient edge computing, maintaining secure data processing without sacrificing performance has become a critical requirement. The proposed system introduces a flexible cryptographic engine implemented on the Zynq-7000 FPGA, capable of supporting multiple hashing algorithms, inclu...
Abdulmunem A. Abdulsamad, S. Répás· Széchenyi István University...· 0 citations
The growing deployment of Internet of Things (IoT) devices, embedded systems, and hardware security platforms has increased the demand for lightweight cryptographic architectures capable of delivering strong security under stringent area and power constraints. Although the Advanced Encryption Standard (AES) is widely a...
M. M. Hasan, Raisa Ahmed, Md. Tawfiq Amin et al.· Discover Electronics· 0 citations
The globalization of semiconductor manufacturing has increased vulnerabilities such as hardware Trojan insertion, overbuilding, reverse engineering, and intellectual property piracy. Logic locking has emerged as an effective countermeasure to protect integrated circuits using secret key activation. The Advanced Encrypt...
P. M, S. P· International Journal of Inf...· 0 citations
The rapid growth of the Internet of Things (IoT) has intensified the demand for lightweight cryptographic solutions that deliver high security without compromising energy and area constraints. This paper presents a highly efficient AES -128 hardware architecture specifically optimised for resource-constrained IoT devic...
Salman Ahmed, N. Ahmad, C. Uttraphan et al.· ASM Science Journal· 0 citations
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