Reliability Assessment of NOEL-V Soft-Core RISC-V on SRAM-Based FPGA Under Radiation

Abstract

This paper presents an implementation of the NOEL-V RISC-V microprocessor in an SRAM-based FPGA. The NASA Core Flight System (cFS) and benchmark applications are used as the software workload. The FPGA was irradiated with alpha particles in vacuum for a preliminary reliability assessment. Different NOEL-V configurations are compared to evaluate trade-offs between computing performance and reliability. The configuration with a richer feature set did not improve processing time but degraded reliability due to the increased circuit area. This result highlights the importance of careful parametrization of RISC-V systems in FPGA to match application requirements. The use of L2 cache also had a negative impact on reliability; however, in this case, it provided a positive trade-off, with up to 40% improvement in mean executions between failure (MEBF).