CoDPlacer: A Fast Approach for Digital IC Placement via Consistency Distillation

Abstract

Modern digital IC placement requires methods that balance placement quality, legality, and runtime as circuit sizes continue to grow. Learning-based generative placers provide a promising alternative to analytical and sequential approaches, but they remain computationally expensive because high-quality generation requires large number of steps. This paper presents CoDPlacer, a consistency-distilled framework for accelerating generative chip placement. The method distills a pretrained diffusion placer into a consistency model for faster macro- and cluster-level placement. Two full-chip placement flows are evaluated: macro placement followed by DREAMPlace standard-cell refinement (conventional method), and a hierarchical flow using standard-cell clustering, boundary-aware expansion, local DREAMPlace optimization, and final assembly. Experiments on 18 IBM benchmarks and five ISPD2005 circuits evaluate inference-step sensitivity, macro placement, and downstream detailed placement. The 128-step consistency model achieves 4.1×, 3.11×, and 7.82× generation speedups relative to the strongest evaluated baseline on clustered IBM, macro-only IBM, and macro-only ISPD2005 benchmarks, respectively, while maintaining competitive HPWL. In conventional full-chip placement, the consistency-distilled model achieves the lowest average HPWL among the evaluated baselines. These results show that consistency distillation provides an effective quality-runtime tradeoff and useful initialization for downstream analytical placement.