Hardware Realization of Multilayer Neural Networks Using Memristor Bridge Synapses

Abstract

The memristor, theoretically predicted by Leon O. Chua in 1971 as the fourth fundamental two-terminal circuitelement, establishes a constitutive relationship between electric charge and magnetic flux. Its practical realizationwas reported by Strukov et al. in 2008 using a nanoscale TiO₂ device, demonstrating resistance switching associatedwith the migration of oxygen vacancies within the oxide layer. One of the most promising applications of memristorsis their use as artificial synapses. In conventional neuromorphic circuits, synaptic weights are generally representedby stored digital or analog values and require separate memory and multiplication circuitry. In contrast, a memristorcan simultaneously provide programmable memory and analog signal modulation through its resistance state. Thecontinuous or multilevel memristance of a device can therefore be used to represent synaptic weights, while anapplied input voltage produces a corresponding weighted current or voltage. However, a single memristor naturallyrepresents a non-negative conductance, creating difficulties in implementing signed neural-network weights,particularly negative and zero synaptic weights.From the investigation of the relationships among flux, charge, and memristance of diverse composite memristorsand analysis of the characteristics of complex memristor circuits, it was found that memristor bridge synapsesprovide an effective solution to this limitation. The bridge architecture employs four memristors in a back-to-backconfiguration, where the differential conductance between the two branches determines the effective synapticweighting. This arrangement enables the realization of positive, negative, and zero synaptic weights while retainingthe compactness and non-volatility of memristive devices.A further challenge is the implementation of neural-network training directly in hardware. Although backpropagationprovides an efficient software learning mechanism, its hardware realization requires gradientcalculation, error propagation, and additional computational resources, which can significantly increase circuitcomplexity. On the other hand, the Random Weight Change (RWC) algorithm provides a hardware-friendly learningstrategy based on iterative trial-and-error weight modification. Accordingly, this work investigates a hardwareorientedneuromorphic architecture based on TiO₂ memristor bridge synapses and RWC learning. The proposedapproach considers the electrical behavior and programmable weighting characteristics of bridge-connectedmemristors and their integration into multilayer neural-network structures. Positive, negative, and zero synaptic operations are realized through differential memristive states, while electrical pulses provide a mechanism forweight programming and signal processing. The RWC learning architecture is subsequently employed todemonstrate circuit-based adaptation of the synaptic weights. Previous studies have shown that, despite requiringmore iterations than back-propagation, RWC can provide substantially faster learning when implemented directlyin hardware, with reported learning times approximately two orders of magnitude lower than software-basedcounterparts. The proposed approach therefore demonstrates the potential of memristor bridge synapses to provideanalog synaptic weighting, and learning within a compact hardware platform, offering a promising route towardenergy-efficient and high-density neuromorphic computing systems.