Characterizing Data Retention in Modern DRAM Devices: On the Influence of Array Access Style on Retention Behavior

Abstract

Dynamic random access memory (DRAM) memory is organized as an array of individual storage cells, each holding data as electrical charge in a capacitor. Due to inherent charge leakage over time, periodic refresh operations are required to preserve data integrity. As semiconductor manufacturing processes scale down and memory density increases, DRAM cells become increasingly prone to charge leakage, making data retention more challenging. To enhance reliability, modern DDR5 memory incorporates error correction code (ECC), which help detect and correct bit errors. Conventionally, refresh commands are issued at a fixed rate across all memory cells, regardless of their actual retention characteristics. However, extensive research has shown that most cells retain data significantly longer than the mandated refresh interval. This uniform refresh strategy results in unnecessary power consumption and reduced memory performance, as resources are spent refreshing cells that are not at immediate risk of data loss. Optimizing the refresh process requires a detailed understanding of cell retention behavior under various conditions. In this work, we present one of the first studies that retrospectively evaluate DDR5 DRAM retention behavior, systematically analyzing the effects of temperature, data patterns, and a previously unexplored factor: array access style. We show that the way memory is written to or read from can impact the retention time of memory cells, potentially accelerating data loss. This finding reveals a new dimension in DRAM reliability and our analysis and findings uncover the effect of on-die ECC on prolonging data retention. These insights provide a foundation for system architects and memory designers to develop more intelligent, adaptive refresh strategies. By accounting for access patterns and on-die ECC behavior, future memory systems can safely relax refresh requirements thus reducing power consumption, improving performance, enabling more accurate, and more efficient retention profiling mechanisms.