Design and Physical Implementation of a Configurable Low-Power RISC-V System-on-Chip for Edge Computing in TSMC 65nm CMOS

Abstract

The proliferation of Internet of Things (IoT) devices necessitates low-power, on-device processing to overcome the latency, security, and power constraints of cloud-based computation. This paper presents the complete design and physical implementation of a configurable, low-power RISC-V System-on-Chip (SoC) tailored for edge computing applications, starting from its conception, going through validation and verification, until the sign-off. The SoC is built on a modular architecture featuring the low-consumption NoX RISC-V core, an AXI4 interconnect, 8 KBytes of on-chip full-custom SRAM, and a set of essential peripherals for external communication and basic real-time operations. Implemented in TSMC 65 nm Low-Power CMOS process, the design follows an industry-standard RTL-to-GDSII flow incorporating low-power techniques such as clock gating. Post-layout results show that the SoC operates at 100 MHz, consuming 14.96mW (149.6 μW/MHz) within a 1 mm2 area, and demonstrates the SoC’s efficiency, with measured power consumption tightly bounded between 37.8 mW and 39.4 mW across diverse workloads, achieving energy costs as low as 2.5 μJ for cryptographic operations and 0.75 μJ for lightweight AI inference. A comparative analysis validates the selection of the NoX core over the CV32E40P, demonstrating a competitive and balanced solution for general-purpose edge computing when benchmarked against other state-of-the-art open-source SoCs.