Aug 2026· Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design· pp. 1-7· 0 citations· 27 references
TL;DR
HotBa is presented, a heterogeneous Mamba accelerator that reduces per-token weight transfer by 82% and redundant computation by 59% via Δ-guided early rejection for wide-tree speculative decoding in Mamba, while a heterogeneous INT8/FP16 core and tree management unit achieve 40.4× area efficiency and 5.18× SSM speedup.
Abstract
Mamba has emerged as a promising alternative to Transformers for on-device LLM inference, offering linear complexity and eliminating KV-cache. However, autoregressive decoding reloads full model weights every token, accounting for 93.2% of total inference energy, with no existing accelerator resolving this overhead. We present HotBa, a heterogeneous Mamba accelerator that reduces per-token weight transfer by 82% and redundant computation by 59% via Δ-guided early rejection for wide-tree speculative decoding in Mamba, while a heterogeneous INT8/FP16 core and tree management unit achieve 40.4× area efficiency and 5.18× SSM speedup with 0.4% area overhead. Synthesized in 28nm CMOS, HotBa achieves 75.32 tokens/s with 1.65× speedup and 7.55× energy efficiency over the state-of-the-art Mamba accelerator.
This paper presents FastTPS, a high performance and low-precision loss method for accelerating the token-phase in LLM inference on general AI accelerators which includes three key components: AI accelerator-enabled reloading-free KV Cache concatenation which decreases memory access overhead as well as enables full fusion of Attention.
Wenzong Yang, Danyang Zhang, Kunteng Cao et al.· arXiv.org· 0 citations
Edge intelligence applications demand high-throughput and energy-efficient hardware accelerators under strict power, latency, and resource constraints in real-time environments. Conventional compute-centric architectures rely heavily on sequential multiply-accumulate (MAC) operations and frequent off-chip memory access, resulting in high energy consumption, increased latency, and bandwidth bottlenecks. These limitations become more pronounced as neural network models scale in size and complexity. While Ternary Content-Addressable Memory (TCAM) offers an alternative through parallel associative search and constant-time pattern matching, it suffers from excessive power consumption and limited adaptability due to continuous match-line activation. This work proposes a hybrid SRAM-TCAM memory-centric deep neural network (DNN) architecture that integrates three tightly coupled subsystems. First, a two-layer autoencoder with ReLU activations compresses 128-bit input feature vectors to 32-bit latent codes, achieving a compression ratio η=4×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\eta = 4\times $$\end{document} and a 75%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$75\%$$\end{document} BRAM saving. Second an on-chip dual-port BRAM data-locality buffer exploits the compressed representation to eliminate inter-layer off-chip DRAM accesses in the critical inference path. Third, a 256×32\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 32$$\end{document}-bit Ternary Content-Addressable Memory array provides O(1) parallel associative inference. A software-only Genetic Algorithm (GA) with Roulette Wheel Selection (RWS) optimizes TCAM configuration offline prior to FPGA deployment; the converged 8,480-bit chromosome is loaded once at startup and remain static during inference, adding zero dynamic power overhead. The proposed architecture, implemented on a Xilinx Artix-7 FPGA, achieves a 42.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$42.3\%$$\end{document} reduction in power compared to a conventional MAC-based baseline (120.5 mW vs. 208.7 mW), an end-to-end throughput of 108.47 Mops reflecting steady-state pipelined operation at 108.47 MHz (2.42×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2.42\times $$\end{document} speedup), and an inference accuracy of 95.3%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$95.3\%$$\end{document} – a 1.5%\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1.5\%$$\end{document} degradation attributable to quantization, evaluated on the benchmark dataset. Power figures are obtained from the Vivado Power Estimator tool (post-implementation) at nominal supply voltage of 1 V. These results demonstrate an efficient and scalable solution for next-generation edge AI inference systems.
Vandana Thakur, V. More, Abhishek Bhatt· Journal of King Saud Univers...· 0 citations
HiKV is a novel algorithm-hardware co-design that exploits KV cache redundancy through hierarchical importance awareness and outperforms state-of-the-art importance-based methods by achieving an additional 1.87x reduction in external memory accesses.
Chao Fang, Jun Yin, Man Shi et al.· IEEE Transactions on Circuit...· 1 citation
LLM impose significant computational and memory demands, creating challenges for energy-efficient inference across platforms ranging from data centers to power-constrained edge devices. Weight precision plays a critical role in balancing inference accuracy, throughput, and energy consumption, while modern LLM workloads exhibit pronounced heterogeneity and tolerance that favors adaptive precision execution. This paper presents CIMERA, a reconfigurable-precision LLM inference accelerator that integrates compute-in-interconnect and memory to mitigate the memory wall and enable precision-aware execution. Compared to Nvidia H100, CIMERA delivers up to $25\times$ and $10\times$ higher energy efficiency for 1B and 13B models, respectively.
We present the Transformer Accelerator (TFA), a synthesizable, parameterizable INT8 memory-to-memory engine for transformer inference. One time-multiplexed datapath handles prompt processing and autoregressive generation. TFA implements matrix multiplication, softmax, RMSNorm, elementwise, and copy/gather operations through eight 512-bit macro-op descriptors. Offline-compiled programs are fetched, validated, and dispatched through AXI interfaces, supporting encoder, decoder, and encoder-decoder models. The RTL combines an output-stationary multiply-accumulate array with ping-pong buffers that overlap DMA and compute, bit-exact reciprocal-square-root and divide units, key-value-cache and embedding addressing, and an abort-safe zero-padding write engine. A UVM environment byte-compares outputs against a bit-exact golden model. Across 25 tests and 34 constrained-random runs, TFA achieved zero mismatches, 100% functional coverage, and 94.96% code coverage. We compiled the t5-small encoder-decoder pipeline for English-to-French, German, and Romanian translation. On ten multilingual proverbs, TFA executed 70,320 descriptors and matched 37.9 MB of golden-model output with zero mismatches. INT8 output matched the floating-point reference token-for-token on five sentences; the rest produced valid alternative translations. Randomized-Hadamard reparameterization recovered about 11 dB of per-tensor INT8 signal-to-noise ratio across layers. The verification configuration achieved about 20x end-to-end speedup over a 22-thread CPU, while larger designs are projected to reduce energy per token by about 1000x. After RAM inference recoding, logic area fell to 2.73 mm2, and the design completed design-rule-clean synthesis and place-and-route on SkyWater sky130. TFA demonstrates end-to-end, bit-exact execution of pretrained transformers using compact hardware and compiler-managed quantization.
With the growing demand of artificial intelligence (AI) applications, large language models (LLMs) have become important workloads in many domains. The question of how to efficiently generate optimal AI chip accelerator designs remains unresolved and challenging. Currently, there is a lack of end-to-end design methodologies for efficient design space exploration (DSE). We propose FSGen, an agile framework for attention-based LLM accelerator generation with an early-stage PPA estimator. FSGen supports fused operator dataflows and sparsity with a diverse design space and finds designs with 1.4x better power efficiency or 10x speedup with similar PPA metrics compared to prior work. Pareto-optimal designs have much better performance over a wide range of LLM benchmarks and have 58x better figures of merit (FoM). Design exploration is also faster due to our PPA estimators, which have better accuracy than prior art and reduce DSE runtime drastically.
J. Mok, Qijun Zhang, Zhiyao Xie· 0 citations
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