Jul 2026· 2026 IEEE International Conference on Quantum Software (QSW)· pp. 89-94· 0 citations· 13 references
Abstract
Quantum circuit optimization plays a critical role in improving the performance of algorithms executed on noisy intermediate-scale quantum (NISQ) devices. While modern quantum compilers provide multiple optimization levels, selecting an appropriate optimization strategy remains a non-trivial task due to the complex interplay between circuit structure and hardware noise. In this work, we present a comprehensive noise-aware evaluation of quantum circuit optimization strategies using a diverse set of 33 circuits, including Quantum Fourier Transform (QFT), Grover's search, Variational Quantum Eigensolver (VQE), and randomly generated circuits. We analyze the impact of different transpiler optimization levels on circuit depth, entanglement (CNOT count), and output fidelity under a realistic depolarizing noise model. Our experimental results reveal that no single optimization level consistently yields the best performance across all circuit types. While aggressive optimization is beneficial for structured circuits such as QFT and VQE, moderate optimization levels often provide a better trade-off between circuit complexity and fidelity for unstructured or randomly generated circuits. These findings highlight that optimization-level selection is inherently dependent on circuit characteristics and cannot be effectively addressed using static or heuristic approaches alone. To address this challenge, we further propose a lightweight learning-based model that predicts the optimal optimization level based on circuit features. The model achieves an accuracy of 93.9% across the evaluated dataset, demonstrating that simple machine learning techniques can effectively approximate optimal compiler decisions without requiring exhaustive evaluation. Overall, this work provides practical insights into optimization behavior in NISQ systems and introduces a scalable approach for adaptive optimization selection, contributing toward more efficient quantum software development.
Simulating quantum error correction (QEC) circuits including non-Clifford gates at scale is important to accelerate progress toward fault-tolerant quantum computing. Here we demonstrate that matrix product state (MPS) techniques can handle many QEC circuits exactly and without restriction on gate types. Crucially, we find that MPS efficiency depends sensitively on implementation choices, and we introduce a series of targeted optimizations that reduce bond dimensions and simulation time by several orders of magnitude compared to naive approaches. We illustrate this with examples including: (a) a rotated surface code quantum memory up to distance 11, (b) logical Bell-state preparation up to distance 9, (c) a 15-to-1 magic-state distillation circuit including hundreds of QEC rounds that we optimize to be simulated with only 11 logical qubits (187 physical qubits) and a maximal bond dimension of 64 in under 40 seconds, and (d) a narrow, deep random circuit that scales linearly with the number of T gates. These results demonstrate the importance of circuit-level optimizations and position MPS as a valuable complement to near-Clifford simulators for QEC circuits.
A. Orioli, Chen Zhao, G. Masella et al.· 0 citations
Quantum benchmarks provide compact measures of performance that are important for evaluating and comparing quantum systems. Circuit-level benchmarks are particularly valuable because they capture the accumulated effects of noise across interacting operations, but existing approaches may require structured gate sets and costly compilation, classical simulation of reference outputs, or subsystem decompositions that do not capture full-register behavior. We introduce Error Per Circuit Layer (EPCL), an overlap-based circuit-level benchmark that estimates an effective layer polarization by applying identical random circuits to two disjoint quantum registers and measuring the overlap between their output states as a function of circuit depth. EPCL avoids classical simulation of ideal output distributions and recovery to a known reference state, and is compatible with arbitrary gate sets, including non-Clifford gates. We derive the expected overlap decay under an ensemble-averaged depolarizing model and identify the assumptions under which the fitted decay parameter represents an effective layer polarization. Numerical simulations show that EPCL recovers the predicted polarization under weak local stochastic noise and remains well described by a single-exponential decay at stronger stochastic noise levels. The simulations further show that coherent errors associated with fixed entangling layers may require Pauli twirling or randomized compiling to produce the expected decay, while inter-register correlations contribute an additional covariance term to the measured overlap. Finally, experiments on IBM quantum hardware demonstrate clear EPCL decay in 8- and 16-qubit implementations. These results support EPCL as a method for measuring aggregate register performance without requiring classical simulation of ideal circuit outputs or restriction to structured gate sets.
Travis Hurant, Arian Vezvaee, Swarnadeep Majumder et al.· 0 citations
A modular implementation in Qiskit that supports non-binary alphabets and incorporates several key enhancements, including a deterministic BBHT-inspired Grover search, domain expansion via ancillary qubits to stabilize amplitude amplification, and circuit-level optimizations that reduce overhead are developed.
R. Cantone, G. Falci, Simone Faro et al.· IEEE International Symposium...· 0 citations
Quantum circuit simulator (QCS) is essential for designing quantum algorithms because it assists researchers in understanding how quantum operations work without access to expensive quantum computers. Traditional array-based QCSs suffer from exponential time and memory complexities. To address this problem, Decision Diagram (DD) was introduced to compress simulation data by exploring the circuit regularity. However, for irregular circuit structures, DD-based simulation incurs significant runtime and memory overhead. To overcome this challenge, we present FlatDD, a parallel QCS that capitalizes on the strength of both DD- and array-based approaches. FlatDD parallelizes the simulation workload at multiple levels and leverages caching to reuse historical results. To further enhance the simulation performance for deep circuits, FlatDD introduces a gate-fusion algorithm to reduce the computational cost. Compared to state-of-the-art QCSs on commonly used quantum circuits, FlatDD achieves 54.35 × speed-up and 1.91 × memory reduction.
Shui Jiang, Hengrui Chen, Rongliang Fu et al.· ACM Transactions on Quantum...· 1 citation
The performance of quantum algorithms on near-term devices is heavily constrained by hardware noise, yet systematic comparisons of algorithmic vulnerability across diverse noise types remain limited. In this study, we benchmark three representative algorithms: quantum teleportation, Grover’s search, and the Quantum Approximate Optimization Algorithm (QAOA), under depolarizing, amplitude damping, phase damping, and thermal relaxation channels. Using exact density-matrix simulations, we characterize algorithmic performance by evaluating state fidelity decay as a function of noise strength. To enable fair, structure-aware comparisons across circuits of varying depths, we introduce a novel metric, the per-gate decay rate. Our analysis reveals that teleportation exhibits the lowest per-gate vulnerability, whereas Grover’s algorithm demonstrates substantially larger, super-linear decay driven by its repeated oracle–diffuser architecture. QAOA displays intermediate and stable noise resilience across system sizes. Finally, we validate our simulation framework through hardware experiments on an IBM Heron processor, demonstrating strong agreement with theoretical predictions (Pearson’s correlation coefficient r = 0.981). This work establishes a quantitative, structure-aware framework for assessing circuit-level noise sensitivity and offers actionable insights for algorithm selection in the noisy intermediate-scale quantum era.
Quantum computing has the potential to accelerate various fields by solving specific problems significantly faster than classical computers. Solving more complex problems generally requires a larger number of qubits. However, current quantum devices are constrained by limited qubit counts and environmental noise. Quantum circuit cutting bridges the gap between the theoretical requirements of large quantum circuits and the practical limitations of current quantum hardware by decomposing large circuits into smaller subcircuits. Tang et al. introduced CutQC, a framework that reduces the number of generated subcircuits and reconstructs the complete quantum state with limited memory consumption. Despite these advances, CutQC faces performance bottlenecks in classical postprocessing, leading to long execution times. To address this limitation, we propose QCutSim, an efficient simulation-based framework guided by insights from the postprocessing stage. It improves performance through optimized simulation and reconstruction strategies, along with computational optimizations such as vectorization and parallelization. QCutSim demonstrates that even consumer-grade systems can efficiently simulate 100-qubit circuits and achieves a speedup of up to 5.1x compared to prior work on the same hardware. In the worst-case scenario of reconstructing dense solution circuits, QCutSim achieves a speedup of 6 to 8 orders of magnitude.
Po-Hsuan Huang, Chun-Yen Tai, Chia-Heng Tu et al.· ACM Transactions on Design A...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.
