Joint Power Allocation and IRS Phase Control Using a Feasibility-Preserving TD3 for Delay-Sensitive Opportunistic NOMA-Based IoT Networks

Abstract

Intelligent reflecting surfaces (IRSs) and hybrid orthogonal frequency-division multiple access/non-orthogonal multiple access (OFDMA–NOMA) can improve connectivity and spectral efficiency in dense cognitive Internet of Things (IoT) networks, but their joint control is challenging under dynamic channel availability and stringent quality-of-service requirements. This paper considers an opportunistic overlay downlink in which a secondary base station jointly determines NOMA power allocation and IRS phase shifts over the idle subchannels. The resulting nonconvex problem includes four hard constraints, the transmit-power budget, idle-channel access, NOMA power ordering, and IRS unit-modulus operation, and two soft probabilistic targets for outage and delay. We develop a feasibility-preserving twin delayed deep deterministic policy gradient method (FP-TD3). Raw actor outputs are mapped through an idle-masked power projection, a monotone NOMA power split, and a unit-modulus phase parameterization, thereby satisfying the four hard constraints for every executed and target action. Outage and delay are incorporated through normalized violation slacks. A heuristic-seeded residual phase representation, projected phase refinement, and candidate-selection shield further improve the per-block reward while preserving hard feasibility. The numerical benchmark assumes perfect instantaneous CSI: before selecting each action, the SBS knows the current direct SBS–SU, SBS–IRS, and IRS–SU channel realizations. Simulations over common channel and availability realizations compare FP-TD3 with penalty-only and projection-based deep reinforcement learning methods, metaheuristics, and non-learning baselines. FP-TD3 achieves the highest sum rate and energy efficiency among the evaluated methods, improves the sum rate by up to 36.99% over TD3+Proj (Joint), maintains zero hard-constraint violations by construction, and requires less than 1 ms per allocation on the tested CPU.