A Review of DC Fault Current Limiters for HVDC Systems: Classification and Design Considerations of Non-Superconducting Topologies

Abstract

The rapid expansion of voltage source converter-based high voltage DC grids has made DC fault protection a critical research priority, due to low network impedance and the absence of natural current zero crossings. DC fault current limiters have emerged as an effective means of suppressing the rapid rise of fault currents and supporting coordinated protection strategies. This paper presents a comprehensive review of non-superconducting DC fault current limiter technologies for high voltage DC applications. A unified taxonomy categorizes existing concepts based on how inductors are realized, inserted, and dynamically reconfigured during fault conditions, while the review traces their historical evolution to highlight key development trends. Representative topologies are analyzed with respect to operating principles, dynamic performance, steady-state losses, and trade-offs among peak current suppression, breaker energy stress, and implementation complexity. Beyond classification, the paper identifies three key design dimensions: inductance selection, magnetic energy management, and coordination with converters and circuit breakers. The review concludes that effective deployment requires coordinated design across these dimensions to balance fault-current suppression, steady-state efficiency, breaker stress reduction, and practical implementation constraints. The paper also presents simulation case studies demonstrating the behavior of representative limiter topologies under common test conditions.