PIM-Pai: Boosting the Performance of Index Structures with Minimal Effort on Processing-in-Memory Architecture

Abstract

Index structures are critical components in the current datacenter. However, their performance is frequently constrained by the memory bandwidth limitations of modern computer architectures. Recently, processing-in-memory (PIM) has emerged as a promising solution to address this challenge. By enabling data processing directly within memory, PIM facilitates the development of more efficient index solutions. Despite the substantial potential of PIM, migrating existing index structures to this paradigm necessitates considerable engineering effort. Furthermore, current PIM solutions have limited capacity and distinctive features, complicating the management of large datasets and the achievement of optimal performance. In this paper, we introduce PIM-Pai, a framework designed to enhance index structures using PIM architecture. PIM-Pai offers plug-and-play capabilities for integrating existing indexes on PIM. PIM-Pai adopts a frontend-backend architecture. The frontend is placed on the PIM side as a cache, while the backend on the DRAM side integrates current indexing methods. This design enables indexes to reap the benefits of PIM acceleration with minimal engineering effort. Additionally, PIM-Pai presents an effective hash index design, a load balancing mechanism, and a low-overhead cache management strategy in the frontend to optimize performance. We implement PIM-Pai on UPMEM, a commercially available PIM device. Evaluations show that PIM-Pai improves index performance by up to 2.5 × with minimal code modifications.