Self-organizing Architecture of Receptron Units: a Hardware-Aware Framework for Edge Intelligence

A Review of AI Computing Hardware for Enabling 6G Wireless Networks: Neuromorphic Chips, NPUs, and TPUs

The introduction of 6G Networks and its deep integration of Artificial Intelligence (AI) necessitates powerful and efficient hardware processors to manage massive data flows, ensure network reliability, and support demanding use cases. To overcome these challenges, the industry is shifting away from conventional processing architectures (CPUs and GPUs) toward specialized hardware accelerators. This paper reviews three critical categories of processing chips: Neuromorphic chips, Neural Processing Units (NPUs), and Tensor Processing Units (TPUs). It also reviews other emerging chips that are still relatively unknown such as Quantum Processing Units (QPUs) and Photonic Integrated Circuits (PICs). Specifically, this paper will review different research tasks and display tables of hardware efficiency and wireless system metrics.

Neural architecture search for optimizing edge computing in IoT devices

The proliferation of Internet of Things (IoT) devices has intensified the demand for efficient and accurate deep learning models capable of operating under stringent resource constraints at the edge. Neural Architecture Search (NAS) offers a promising avenue to automate the design of optimized neural networks tailored for edge computing environments. This paper investigates the application of NAS for optimizing neural network architectures deployed on IoT edge devices, balancing accuracy, latency, and energy efficiency. We propose a multi-objective NAS framework that incorporates hardware-aware constraints specific to typical IoT edge platforms. Experimental results on benchmark datasets demonstrate that NAS-generated models outperform conventional architectures in terms of inference speed and power consumption, while maintaining competitive accuracy. Our findings highlight the potential of NAS as a vital tool for enhancing edge intelligence in IoT systems.

Design-Time Optimization of Deep Neural Networks for Intermittent Learning on Microcontrollers

We present a method for designing deep neural networks (DNNs) for intermittent, energy-autonomous, on-device learning on microcontroller units (MCUs). In mobile applications where the energy can run out, e.g., when solar-powered, executing artificial intelligence (AI) faces a technical issue as learning can be interrupted at any time. Our approach combines a hardware-aware energy prediction model with multi-objective optimization (MOO), enabling offline DNN optimization at the design stage without repeated deployment and online testing on the target MCU. Our proposed energy predictor estimates per-layer energy consumption for both DNN inference and training, including the intermittent checkpointing overhead, based on implementation-specific compute and memory features extracted from the DNN model. We validate our approach using autoencoders for anomaly detection on a Cortex-M4 MCU, where our predictor achieves a weighted absolute percentage error of 16.6%, which is sufficient for reliable architecture selection under intermittency constraints. As a result, this work bridges the gap between MOO, automated DNN design, deployment on energy-harvesting systems, and intermittent learning, truly enabling autonomous AI at the edge.

Leveraging ECRAM for Edge Continual Learning

Several edge computing platforms, such as autonomous vehicles and smart sensing devices, need to adapt to dynamic environments in real time by learning from new data in the field. Continual learning has emerged as a promising solution for edge training, by incorporating techniques that successfully combine a highly summarized version of previously trained data (to avoid catastrophic forgetting) with recently sensed data. However, as is the case with other ML algorithms, continual learning generates significant data movement between general-purpose CPUs/GPUs and memory, impacting the suitability of continual learning for edge platforms. In-memory computing (IMC; also known as processing-using-memory) can curtail this waste and make continual learning feasible at the edge, but it faces two unique challenges: (1) IMC architectures make use of noisy computation operations that significantly harm training accuracy; and (2) IMC architectures have poor and often incomplete support for resource-efficient training. To address these challenges, we propose CLASP (the Continual Learning Acceleration System Platform), which to our knowledge is the first end-to-end system with IMC acceleration for continual learning. The hardware and software of CLASP are co-designed to support a wide range of continual learning algorithms, through software-visible assembly-level instructions that can be incorporated without constraints into ML-based algorithms. CLASP is designed around a back-end-of-line (BEOL) compatible ECRAM device that we fabricate, which can overcome the challenges of IMC-based training using other emerging memory devices. We show that CLASP with ECRAM approaches the accuracy of in-GPU training, while delivering a speedup of 67x and energy savings of 132x for learning without forgetting and experience replay using MNIST.

Modular Neural Networks: A Brain-Inspired Architecture via Dynamic Topology, Continuous Fuzzification, and Global Energy Arbitration

SynapticOS: An Inference-First Runtime Architecture for Neural Processing Units on Resource-Constrained Microcontrollers

Microcontrollers with on-die neural processing units (NPUs) have become mainstream, but the system software hosting them has not: production combinations of Zephyr or FreeRTOS with TensorFlow Lite Micro treat AI inference as an application-layer library, leaving memory fragmentation, accelerator-state hygiene, and model-lifecycle guards as recurring application-developer concerns. We present the Phase 1 foundation of SynapticOS, an open-source runtime built on Zephyr that treats inference as a first-class workload. It contributes four cooperating subsystems: (1) a tensor-aware bump allocator with 16-byte DMA-aligned persistent and ephemeral lifetimes sharing a single arena, achieving constant-time allocation (~154 cycles per call, ~78,000 allocations per second at 150 MHz, invariant across tensor sizes) with zero fragmentation by construction; (2) a four-state hardware abstraction layer for the NPU and DSP, implemented by a deterministic software stub (for CI under QEMU) and a Neutron-flavoured backend (for the NXP MCXN947); (3) a three-state model lifecycle registry with duplicate-name detection, idempotent load/unload, and hot-swap guards; and (4) a four-mark cycle-accurate profiler. We evaluate on the NXP FRDM-MCXN947 (dual Cortex-M33 at 150 MHz) and the qemu_cortex_m3 emulator. Build footprints are 67 KB flash / 184 KB SRAM on FRDM (shell, 128 KB arena) and 24 KB flash / 28 KB SRAM on QEMU (no shell, 8 KB arena). End-to-end inference brackets through the deterministic stub kernel measure 1,038 us on FRDM and 781 us on QEMU for a 16x16x3 INT8 input; these are baseline overhead numbers, not Neutron silicon measurements, which arrive with the real SDK invoke path in Phase 2. A 61-test suite across 10 ZTEST suites passes 100% in 6.6 s on the CI emulator path. SynapticOS is released under Apache 2.0 at https://github.com/Dimitrios-Kafetzis/SynapticOS