#edge computing
Open access
Comparative Analysis of RISC-V Custom Vector Extensions for Edge Neural Network Inference
Sep 2026 · Zenodo (CERN European Organization for Nuclear Research)
Abstract
Executing deep learning models on sub-watt edge devices is severely constrained by memory bandwidth limits and control-path overheads. This research presents a custom hardware-software co-design using an open-source 32-bit RISC-V architecture optimized with specialized packed low-precision (INT8/INT4) vector extensions. Synthesized on a Xilinx Artix-7 FPGA fabric, the modified microarchitecture reduces execution latency by 3.2x and dynamic energy consumption by 41% for edge neural ne[i]twork workloads (MobileNetV2, YOLO-Tiny). Despite a 14% increase in LUT utilization and a 5% drop in maximum operational clock frequency, the core demonstrates a net 2.8x improvement in operational compute efficiency (TOPS/W).