Frontier-Aware Compensated Truncated Multiplier for Energy-Efficient Edge-AI VLSI Datapaths

Abstract

Approximate multiplication is attractive for VLSI accelerators used in image processing, digital signal processing, and edge artificial intelligence because many workloads can tolerate bounded numerical error in exchange for reduced switching and arithmetic complexity. This work presents a frontier-aware compensated truncated multiplier (FA-CTM) that removes the lowest partial-product columns while preserving only the boundary, or frontier, column for a compact activity estimator. The frontier population is mapped to a quantized correction term that is added to the retained partial-product sum. Unlike uncompensated truncation, the proposed method targets the systematic negative bias produced by discarded partial products without reconstructing the full lower array. Exhaustive evaluation of all 65,536 unsigned 8-bit input pairs shows a mean error distance of 3.055, normalized mean error distance of 4.70×10⁻⁵, maximum error distance of 13, and mean relative error distance of 1.92×10⁻³. Relative to simple four-column truncation, FA-CTM reduces MED and NMED by 75.1%, MRED by 65.9%, and maximum error by 73.5%. In a 64-term multiply-accumulate benchmark, the mean relative output error falls from 0.0763% to 0.0132%. The partial-product generation domain uses 58 terms instead of 64 and exhibits a 9.35% reduction in measured partial-product toggle events under random operands. A 16-bit sampled validation further shows that frontier compensation remains effective when the truncation boundary is scaled. These results indicate that low-cost error-shaping around the truncation frontier is a practical design direction for energy-conscious VLSI datapaths.