Sep 2026· IEEE International Conference on Application-Specific Systems, Architectures, and Processors· pp. 175-176· 0 citations· 9 references
Abstract
Currently, the prevalence of heterogeneous multicore architectures even in real-time safety-critical embedded systems is rising, as an increasing number of applicationspecific accelerators are introduced into the core architecture to tackle more and more complex problems. This does create a challenge for the modern developer, as the hardwaresoftware mapping is consequently becoming more complex as well, increasing development times. The developer can be assisted by leveraging automated scheduling algorithms, which calculate optimal hardware-software mappings and execution orders. As safety-critical timing constraints are a critical part of realtime embedded systems, being able to quantify the deterministic safety-compliance of the system at compile-time is a considerable upside of static scheduling approaches. However, to be able to fully incorporate static scheduling in the development cycle of safety-critical systems, solutions that allow for automated safetycompliance are needed. In this paper, we show how existing static scheduling methods can be extended to calculate schedules with minimal overall latency while respecting one or more intermediate deadlines. We utilize this to achieve full deadline compliance for up to three simultaneous intermediate deadlines with an average accuracy of 99% for easy problems, and up to 69.3% for very hard problems.
RunSoC 2.0 improves the realism of early-stage MPSoC analysis while retaining practical solution times for large automotive workloads, and incorporates cluster-aware communication and memory modeling.
D. Krüger, Lucas Mauser, Stefan Wagner· 0 citations
(English) High-performance computing (HPC) platforms are evolving towards increasingly complex architectures: many-core CPUs with multi-level NUMA hierarchies, heterogeneity with multiple classes of accelerators and higher-capacity interconnects. The increasing complexity and variety of resources in these machines make...
Task-based HPC runtimes are typically tuned under a performance-first requirement with the assumption that the fastest configuration requires all available cores. This paper asks whether that assumption holds, and whether high performance can be achieved with fewer resources. We study this question using SWITCHES, a ta...
Hui-Min Zhang, Andreas Diavastos· Workshop Proceedings of the...· 0 citations
This work presents a lightweight and modular proof technique for verifying eventual progression guarantees for Rust async runtimes and realizes this proof technique as a set of static analyses for Rust and uses these to verify eventual progression of several key components of multiple Rust async runtime implementations...
Yan-Ze Li, I. Beschastnikh, Alexander J. Summers· 0 citations
Janus is presented, an LLM-assisted framework that synthe-sizes custom instructions integrated into the Ibex RISC-V core while keeping correctness outside the agent, demonstrating a practical path for using LLMs to explore ISA specialization without making the agent part of the trusted correctness boundary.
Kamera is presented, a system for testing CCPs that uses partial simulation to execute the code of multiple interacting controllers against a lightweight model of the Kubernetes runtime and achieves a 1,781× speedup over existing cluster-based controller testing approaches.
Tim Goodwin, Lindsey Kuper, Andi Quinn· Proceedings of the ACM SIGOP...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.