Bridging the Gap Between Pedagogical and Practical RISC-V Systems: A Reproducible FPGA Implementation and Verification Flow

Abstract

Conventional undergraduate computer architecture curricula typically prioritize microarchitectural theory validated solely through logic simulation, often omitting the complex engineering layers required for physical hardware deployment and high-level language execution. This work addresses this disparity by presenting the end-to-end design, implementation, and physical validation of a fully functional RISC-V (RV32I) soft-core processor targeting the Intel Cyclone V FPGA. To bridge the gap between pedagogical models and operational embedded systems, the project adopts a rigorous engineering methodology encompassing a containerized toolchain for cross-platform reproducibility, a robust memory mapped I/O architecture, and a multi-tiered verification strategy leveraging GHDL, Cocotb, and the RISC-V Architectural Compliance Suite (RISCOF). By integrating vendor-specific Intellectual Property (IP) for memory management and clock distribution, the design resolves critical timing and signal integrity constraints often overlooked in educational settings. The resulting implementation achieves a maximum operating frequency (Fmax) of 123.4 MHz with a minimal logic footprint of only 9% ALM utilization, successfully executing bare-metal C applications. These results demonstrate that applying industrial- grade verification and synthesis workflows transforms academic prototypes into reliable, deployable hardware.