This work proposes a low-complexity Feature Selection NN DPD architecture that employs an offline feature-engineering pipeline based on the Least Absolute Shrinkage and Selection Operator and the Minimum Redundancy Maximum Relevance algorithm to construct a compact and informative input representation.
Abstract
Due to the continuous increase in communication bandwidth and the use of highly efficient yet nonlinear power amplifiers, Digital Predistortion (DPD) algorithms are becoming increasingly complex. In particular, neural network (NN) based DPD approaches using Phase-Normalized NN architectures often incur substantially higher computational costs than widely deployed polynomial-based methods, such as the Memory Polynomial (MP) and Generalized Memory Polynomial (GMP) models. To bridge this gap between research performance and practical implementation, we propose a low-complexity Feature Selection NN DPD architecture. The proposed method employs an offline feature-engineering pipeline based on the Least Absolute Shrinkage and Selection Operator (LASSO) and the Minimum Redundancy Maximum Relevance (MRMR) algorithm to construct a compact and informative input representation. Using measured wideband FR3 power amplifier datasets that are publicly released with this work, we demonstrate up to 30% reduction in computational complexity while maintaining comparable linearization performance.
Simulation results show that while CNNs offer a favorable trade-off between linearization performance and model complexity, GRU and LSTM architectures achieve the best overall NMSE and ACPR improvements, albeit with a higher number of parameters.
Hafsa Laakouri, M. Ouadefli, A. Tribak et al.· EPJ Web of Conferences· 0 citations
Digital predistortion (DPD) compensates for nonlinear distortions caused by RF power amplifiers (PAs) for efficient and linear signal transmission. Although generalized memory polynomial (GMP) models are frequently used for DPD, their dimensionality increases with memory depth, which raises computational costs and deteriorates numerical conditioning. Although batch principal component analysis (PCA) reduce this dimensionality, it is unable to adjust to PA characteristics that change over time. We present IPCA-GMP, a framework that combines GMP modelling with incremental PCA (IPCA), where updating mean and covariance estimates recursively and executing rank one eigenspace updates from streaming data. The eigenspace update achieves $\mathcal{O}\left(k D^{2}\right)$ per block cost without a complete eigen decomposition by using a rank one perturbation procedure on the current eigen basis. The results demonstrate that IPCA-GMP compresses the model dimension from $D=224$ to $k=20 (11 \times$ compression), achieving a normalized mean square error of -39.02 dB within 0.41, dB of the full GMP baseline. The condition number is better than $3.3 \times 10^{26}$ to 1,570, and with just 1.8% FLOP overhead compared to the baseline GMP solver, the per-update complexity drops from $\mathcal{O}\left(N D^{2}+D^{3}\right)$ (batch PCA) to $\mathcal{O}\left(D^{2}+k D^{2}\right)$.
Girish Chandra Tripathi, Anindya Saha· International Conference on...· 0 citations
This work presents a direct-learning architecture of a neural network (NN) digital predistortion (DPD) linearizer for a multiple-input multiple-output (MIMO) system while maintaining low complexity compared to a single-input single-output (SISO) system.
This article proposes a novel, low-rate digital predistortion (DPD) for sub-6-GHz 400-MHz modulated signal transmission. In this model, a low-rate input signal is concurrently fed into multiple parallel cascaded model branches to generate the low-rate predistorted signal. Each branch contains: a dual-function finite impulse response (FIR) filter for interpolation and memory effect compensation, multiple parallel Volterra series-based submodels that are selectively activated based on the current input state and are optimized in complexity by a pruning algorithm, and low-rate filters. Additionally, a model parameter extraction method is introduced for this model. Based on this model, a high-precision DPD system can be obtained with low system processing rates. Experimental validation was performed using 5G new radio (NR) signals with 400-MHz modulation bandwidth on a 3.4–3.8-GHz gallium nitride (GaN) Doherty power amplifier (PA) at low system processing rates of 983 and 491 MSPS, respectively. Measurement results demonstrated that the proposed technique achieves good performance with lower complexity than existing models, with a normalized mean-square error (NMSE) and an adjacent channel power ratio (ACPR) of approximately −41 dB and −46 dBc at 983 MSPS, respectively, and an NMSE of approximately −40 dB at 491 MSPS.
Xiaoyu Lu, Tong Tong, Yucheng Yu et al.· IEEE transactions on microwa...· 0 citations
Wideband transmission in current Wi-Fi 7 (IEEE 802.11be-evolution) and 5 G cellular communication systems has enabled significantly higher throughput in the 6-GHz band (5.925–7.125 GHz) worldwide. However, the use of wider bandwidths introduces several critical challenges for both Wi-Fi and 5 G networks. One of the most important challenges is maintaining high energy efficiency under wideband operation. To achieve high energy efficiency, power amplifiers (PAs) should operate in or near saturation, where nonlinear distortion is introduced and degrades transmitter performance. In this article, dynamic compensation techniques based on digital and RF predistortion are investigated to mitigate power-amplifier (PA) nonlinearity in broadband wireless transmitters. The work addresses key challenges in Wi-Fi 7 and 5G systems, including wide transmission bandwidths, high peak-to-average power ratios, and temperaturedependent PA behavior. A derivative-free adaptive algorithm with dual-objective optimization is developed to track and compensate for temperature-induced PA variations using either digital predistortion (DPD) or RF predistortion (RFPD). In additions, a metalearning framework is incorporated to enable rapid convergence across multiple operating environments. Finally, circuit- and sys-tem-level design considerations are presented to facilitate practical and energy-efficient implementations.
Yiyang Gao, Wei Gao· IEEE Circuits and Systems Ma...· 0 citations
