A compact and extensible hardware platform for automated system-level power measurement of embedded devices that enables automated benchmarking and reproducible experiments across multiple firmware variants, suitable for research, prototyping, and educational environments.
Abstract
Accurate power measurement is not only essential for evaluating the energy efficiency of modern embedded and semiconductor systems, but power draw is an important proxy during stress testing. Industrial semiconductor test equipment, however, is often expensive and difficult to integrate into flexible experimental workflows. This paper presents a compact and extensible hardware platform for automated system-level power measurement of embedded devices. The proposed setup integrates a Raspberry Pi controller, a precision current measurement device, and a microcontroller-based Device-under-Test (DUT). The system supports automated firmware deployment, synchronized device execution, and high-resolution current acquisition. A lightweight HTTP-based interface allows remote clients to upload firmware binaries and retrieve measurement results. This design enables automated benchmarking and reproducible experiments across multiple firmware variants. The platform is implemented using accessible hardware components and open-source software tools, making it suitable for research, prototyping, and educational environments. We describe the architecture of the platform, the automated testing workflow, and potential application scenarios, including firmware energy profiling and regression testing.
The paper synthesizes design principles for constructing automation frameworks that maximize measurement throughput while maintaining calibration traceability, and identifies the key challenges of timing synchronization, instrument state management, error recovery, and data provenance that differentiate professionally engineered automation systems from ad hoc scripts.
Robert Quainoo· International Journal of Eng...· 0 citations
This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the PYNQ-Z2 FPGA board, the core operates at a maximum frequency of 90 MHz, achieving a performance of 0.18 DMIPS/MHz while utilizing only 1,134 LUTs and 406 Flip-Flops. The entire system consumes a highly competitive dynamic power of 18 mW and features a full software ecosystem capable of running C code via the standard RISC-V GCC toolchain. Operational integrity was verified through physical hardware testing and the Dhrystone benchmark alongside integrated AMBA APB3 UART, SPI, and PWM peripherals. These features make NexusV a viable Intellectual Property (IP) core for low-power control units in battery-powered devices.
Prithiviraj Rajalingam, Sudeshna Shettygari, S. S. et al.· 2026 International Conferenc...· 0 citations
High-resolution energy data is increasingly central to Industry 4.0, where electrical signals such as three-phase voltage and current carry rich information about machine condition, tool wear, and process dynamics. Capturing this information in practice remains difficult: commercial power analysis are largely proprietary, offer limited or no access to high-sampling rate data for transient analysis, restrict access to raw waveform data, and offer no customization, while general-purpose open hardware lacks the front-end accuracy, isolation, and robustness required for industrial measurement. This paper presents Autonomous Energy Monitoring System (AEMS), an open-source, low-cost, and modular platform supported by a host, edge-gateway, and optional cloud software stack that enables autonomous, long-duration acquisition independent of a continuously connected host and thereby closes this gap by combining research-grade fidelity with industrial deployability. The system acquires three-phase voltage and current through an isolated front-end and a 24-bit, simultaneously sampling analog-to-digital converter, managed by a dual-core architecture that separates deterministic acquisition and on-board logging from host communication and control. Industrial interfaces (Ethernet, RS-485/Modbus, and BLE) together with hardware-level synchronization enable scalable, time-aligned acquisition across multiple machines, supported by a complete host, edge-gateway, and optional cloud software stack. We validate the platform on a three-axis CNC machining center, where it resolves spindle, feed-drive, rapid-traverse, and material-removal energy states and detects feed-rate changes as small as 50 mm/min. By releasing the full hardware and firmware openly, this work aims to democratize access to high-fidelity energy monitoring for both researchers and small and medium-sized manufacturers.
Vignesh Selvaraj, A. Nagaraj, Shengyuan Zhang et al.· 0 citations
This paper presents the design and evaluation of a light-weight RISC-V-based microcontroller targeted for embedded and real-time applications. Leveraging the modularity and openness of the RISC-V instruction set architecture (ISA), the proposed single-cycle MCU integrates the RV32I base ISA with custom bit manipulation instructions that reduce instruction count and improve execution efficiency, peripheral subsystems, and a datapath-optimized design to deliver energy-efficient performance. Major peripherals, including UART, GPIO, timers, and interrupt controllers, are seamlessly included in a memory-mapped manner to simplify system development. The MCU was synthesized in Verilog HDL and implemented on the Xilinx Artix-7 FPGA platform. Moreover, functional correctness is verified using standard RISC-V compliance tests. Experimental results demonstrate favorable trade-offs among performance, resource consumption, and power efficiency when compared with available RISC-V soft cores and commercial microcontrollers.
This paper presents an IoT-based embedded system for automated digital IC testing, addressing the high cost and limited flexibility of conventional Automated Test Equipment (ATE). The proposed system adopts a distributed architecture consisting of one master controller and up to three testing nodes interconnected via a CAN bus network. Each node performs functional verification using truth-table comparison and electrical fault detection including short-circuit identification via ADC-based voltage monitoring. The system integrates real-time data acquisition, an HMI touchscreen for local operation, and a desktop application for remote monitoring via MQTT over WiFi. Experimental results on multiple 74HC series ICs demonstrate: (i) 100% short-circuit detection accuracy, (ii) 93.3% functional fault detection accuracy, (iii) CAN bus communication latency under 10 ms, and (iv) successful parallel testing across three nodes simultaneously. With a total hardware cost under $300, the proposed solution provides a scalable, cost-effective alternative for IC testing in educational laboratories and small-scale production environments.
Nguyen Van Thai, Tran Thu Ha, B. Bao et al.· 2026 11th International Conf...· 0 citations
With the increasing demand for operating system determinism in fields such as industrial automation and high-frequency trading, it is difficult for general-purpose Linux systems to meet microsecond-level control requirements due to the nonreal- time nature of their scheduling strategies. This paper proposes a Linux kernel real-time modification scheme based on the PREEMPT_RT patch and optimizes user-space system call overhead by combining VDSO (Virtual Dynamic Shared Object) technology. To overcome the limitations of pure software testing methods in terms of clock accuracy and system load interference, this paper innovatively designs a "Hardware-in-the-Loop" (HIL) latency testing method based on a PCIe interface FPGA board. This method uses the FPGA onboard 125MHz high-stability crystal oscillator as an independent time base to periodically read and verify the hardware counter through the kernel high-resolution timer, accurately quantifying the system scheduling jitter. Experimental results show that under the Fully Preemptible mode, the system's scheduling latency in multi-tasking loads is significantly reduced, meeting hard real-time application requirements.
Nan Sang, Jiazhuang Lin, Bingyan Zhu· International Conference on...· 0 citations
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