Design Space Exploration of Accelerating Monolith Hash on Hardware for STARK

Abstract

Zero-Knowledge Proof (ZKP) systems, particularly zk-STARKs, incur substantial computational overhead, where hash functions constitute a significant portion of the total cost. Among various ZK-friendly hash functions, Monolith achieves strong performance in both plaintext domain and ZK domain, making it a promising candidate for efficient ZKP implementations. However, its arithmetic-oriented design introduces challenges for hardware realization, including inefficient resource utilization and difficulty in balancing performance with area and power consumption. In this work, we present a hardware-oriented design for accelerating the Monolith hash function on FPGA. We propose a dual-architecture framework consisting of a serial architecture and a parallel architecture to address different performance and resource constraints. To improve hardware efficiency, we introduce several optimizations, including LUT-based constant multipliers using non-adjacent form (NAF) encoding, a lazy reduction strategy leveraging the Mersenne prime structure, and a reformulation of the Concrete layer to enable efficient computation reuse. Experimental results demonstrate that the proposed designs significantly reduce hardware resource usage and power consumption compared to existing implementations, while maintaining competitive performance. In particular, the serial architecture reduces DSP utilization by up to 97.87%, and the parallel architecture achieves a 1.11 \(\times\) speedup with moderate resource overhead on Zynq 7020 FPGA. Moreover, the proposed designs achieve 51.15% improvements in area-time efficiency. These results demonstrate that the proposed serial and parallel architectures provide resource-efficient and throughput-oriented design points for FPGA-based hash acceleration in STARK proving systems.