A 492.8-TOPS/W STT-MRAM Sparsity-Adaptive Compute-in-Memory Macro for Edge AI Inference

Abstract

The rapid proliferation of intelligent sensors has led to increased latency and privacy risks when processing data on a remote server. This work proposes a spin-transfer torque magnetic random access memory (STT-MRAM) compute-in-memory (CIM) macro to enhance inference efficiency for an artificial intelligence (AI) model on the edge device. A sparsity-adaptive design is presented, featuring coupled-1T1M (c-1T1M) computing cells to eliminate bit-level activation computing power overhead and suppress pattern-dependent deviations in the result. An activation-aware voltage comparator array (AA-VCA) reduces power consumption by up to <inline-formula> <tex-math notation="LaTeX">$56{\times }$ </tex-math></inline-formula> and improves sensing margin by <inline-formula> <tex-math notation="LaTeX">$13{\times }$ </tex-math></inline-formula>. At the system level, a hybrid-granularity sparsity workflow accelerates inference and aligns well with compact analog CIM architectures. In addition, a hardware-implemented variational autoencoder (VAE) is deployed to enhance processing capabilities. The test chip is fabricated in 28-nm CMOS with 60-nm MTJ, achieving energy efficiencies of 712 TOPS/W for image classification and 492.8 TOPS/W for anomaly detection, along with an accuracy of 96.3% and an <inline-formula> <tex-math notation="LaTeX">$F1$ </tex-math></inline-formula> score of 0.97.