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Deep Permutation Networks: Layerwise Invariant Manifolds, Closed-Form Attractor Splicing, and Zero-Backpropagation Topological Learning

Sep 2026 · Zenodo (CERN European Organization for Nuclear Research)
Ferroelectric and Negative Capacitance Devices

Abstract

For four decades, deep artificial neural networks have relied on continuous vector spaces, dense floating-point General Matrix Multiplications (GEMM: hl+1 = σ(Wlhl + bl)), and gradient-based backpropagation. While effective in data centers, this paradigm incurs severe thermodynamic, memory bandwidth, and numerical stability bottlenecks in ultra-low-power edge computing, implantable micro-sensors, and real-time robotic controllers. We formulate Deep Permutation Networks (DPN), an entirely discrete, topological learning paradigm operating over stratified symmetric groups and factorized Young subgroups Sλ = Sλ1 × ... × SλK. Originating from foundational theoretical discoveries on invariant sub-manifolds, DPN completely eliminates continuous GEMMs and backpropagation. Continuous multi-modal data streams are ingested via a Unified Parallel-Branch Ingestion Architecture (ParallelBranchDPNClassifier): a core Young subgroup ordinal sorting branch captures monotonic order invariants, while parallel spectral, variational, and geometric filter branches—incorporating 3D/2D/1D discrete Laplace-Beltrami operators, Fast Walsh-Hadamard transforms, Takens delay-permutation embeddings, Chebyshev orthogonal projections, AC Fourier harmonics, and selectable foreground bounding-box isolation—evaluate feature representations with strictly 0.00 arithmetic MACs. Each neural layer acts as an invariant algebraic permutation manifold propagating activations as zero-FLOP phase rotations, while inter-layer communication is governed by cycle splicing in O(1) time. Training executes without chain-rule gradients via single-pass topological transposition steering into target Tarski attractor basins (Π2 = Π). When evaluated via post-synthesis standard-cell gate-level simulations in TSMC 28 nm HPC+ CMOS (modeled via CACTI 7.0 and Cadence Genus), a 3-stage pipelined APM-RAM controller operates at 4.5 GHz with 0.52–1.12 ns latency, dissipating only 6.6 μW – 23.4 μW and requiring 14.8–48.2 fJ per inference (>15,000× – 40,000× lower energy than iso-process systolic GEMM accelerators). Extensive empirical evaluations across diverse physical and digital modalities—including 3D LiDAR point clouds, 3D volumetric medical CT, industrial 2D laser triangulation profilers, acoustic speech resonances, 3D RGB-D spatial scenes, 16-channel BCI EEG telemetry, UCI benchmarks, and dense text embeddings—confirm strictly 0.00 arithmetic MACs, high classification accuracy, sub-kilobyte static memory footprints (1.8–24.6 KB), and exact mathematical determinism.

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