Secure RISC-V architectures for brain-inspired computing

Abstract

Modern Cyber-Physical Systems (CPS) demand high computational capability, strong security guarantees, and energy-aware operation, particularly in embedded, mobile, and autonomous platforms such as robotics, intelligent vehicles, and industrial controllers. Addressing these requirements calls for heterogeneous System-on-Chip (SoC) architectures that balance performance, efficiency, and security while supporting flexible on-device artificial intelligence (AI) execution. This thesis proposes a heterogeneous, high-performance RISC-V–based architectural template integrating a general-purpose host processor, a programmable acceleration cluster, and a Root-of-Trust (RoT), providing the system context for the design and evaluation of security and AI acceleration mechanisms. To strengthen runtime security, the thesis investigates two hardware-assisted Control-Flow Integrity (CFI) approaches for RISC-V systems. The first introduces CVA6-CFI, the first hardware-extended application-class core implementing the recently ratified Zicfiss and Zicfilp specifications, achieving robust forward- and backward-edge protection with only 1.0% area overhead and up to 15.6% performance overhead on the MiBench automotive subset. The second approach leverages the OpenTitan RoT as a firmware-based CFI co-processor, enforcing control-flow policies externally to the host pipeline with minimal area cost and less than 10% execution overhead. Together, these approaches represent complementary design points for secure RISC-V SoCs. Among emerging on-device AI paradigms, brain-inspired spiking neural networks (SNNs) offer compact and event-driven computation. To avoid reliance on fixed-function accelerators, this thesis introduces SpikeStream, a software-defined neuromorphic acceleration framework that exploits RISC-V sparse streaming ISA extensions to accelerate SNN inference on programmable cores. SpikeStream achieves up to 7.3× speedup and 5.7× energy savings over SIMD baselines, while matching or outperforming specialized neuromorphic processors. Finally, the thesis demonstrates the integration of an industry-grade LPDDR4 memory subsystem within the proposed heterogeneous RISC-V SoC, highlighting the area and integration trade-offs required to sustain high off-chip bandwidth. Collectively, these contributions advance secure, flexible, and efficient RISC-V architectures for next-generation CPS and edge AI applications.