This work proposes an edge-oriented hybrid fault-space restructuring methodology that utilizes UMAP-based embeddings and hierarchical clustering to group overlapping fault conditions into robust hybrid representations, ensuring a highly viable execution on resource-constrained devices once the classifiers are trained.
Abstract
Fault diagnosis in power electronic systems is challenging when fault categories geometrically overlap within the measurement space, limiting class separability and introducing classification ambiguity. This work proposes an edge-oriented hybrid fault-space restructuring methodology that utilizes UMAP-based embeddings and hierarchical clustering to group overlapping fault conditions into robust hybrid representations. Subsequently, supervised machine learning models execute the final classification over this optimized space. Validation was conducted using a large-scale synthetic dataset generated via real-time hardware-in-the-loop (HIL) simulation, evaluating electrical measurements from three-dimensional RMS values to 60-dimensional instantaneous waveforms. Tested with Decision Tree and Random Forest algorithms, the restructuring strategy significantly improves robustness under geometric ambiguity compared to conventional classification without space restructuring. Specifically, low-dimensional measurements achieved F1-score improvements of approximately 72% and 46% for the Decision Tree and Random Forest algorithms, respectively, while high-dimensional measurement configurations still exhibited significant improvements of 36% and 52%. Consequently, these results confirm that the combined restructuring and classification pipeline is highly effective across the analyzed measurement dimensionalities, establishing a dependable cluster-based diagnostic strategy that enhances classification robustness while accepting a trade-off in individual fault-isolation granularity. Finally, hardware deployment experiments on a Raspberry Pi 4 platform demonstrated the feasibility of executing the trained classifiers for real-time inference under constrained computational environments. The experimental evaluation validated real-time execution capabilities, achieving sub-millisecond inference latencies (as low as 0.32 ms), a memory footprint under 0.14 MB, and processing rates exceeding 2600 inferences per second using lightweight Decision Tree classifiers. Ultimately, these findings indicate that the proposed strategy improves fault detection across the evaluated measurement configurations while ensuring a highly viable execution on resource-constrained devices once the classifiers are trained.
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