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Zihan Liu

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Book Open access Oct 2026

AlphaCu: A Transformation-Driven Synthesis Framework for LLM-Based GPU Kernel Generation

Large language models show promise for code generation, yet their effectiveness in producing high-performance GPU kernels remains insufficiently understood. Recent agentic workflows improve over direct prompting through specialized generation roles and execution feedback, but our characterization of a representative wo...

Yang-Jie Zhou, Xing-Chen Ma, Zi-Han Liu et al. · 0 citations
Preprint Aug 2026

Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

Vision-language-action (VLA) models have emerged as a key component in embodied AI. Among existing approaches, diffusion-based VLA models achieve superior motion quality and generalization. However, diffusion-based VLA models are compute-intensive and must run at high control frequency, e.g., 50-200 Hz. Thus, it impose...

Zheng Liu, Zeyu Guo, Zihan Liu et al. · 1 citation
Preprint Sep 2026

Atlas: Algorithm-Hardware Co-Design for On-Device City-Scale 3D Gaussian Splatting in VR

Atlas is presented, an on device city scale 3DGS rendering framework that enables scalable rendering without runtime Internet access and proposes temporal aware LoD search and stereo rasterization to avoid redundant computation in VR.

He Zhu, Zheng Liu, Xingyang Li et al. · 0 citations
Jul 2026

Kaleido: Algorithm-Hardware Co-Design for Video Diffusion Transformers by Exploiting Latent Space Correlations

Kaleido is presented, an algorithm hardware codesign that accelerates all operations in vDiTs by exploiting channel-wise spatiotemporal correlations in latent space and skips redundant computations by reusing partial results while preserving higher generative quality than prior methods.

Wen-Xuan Miao, Haosong Liu, Weiming Hu et al. · 1 citation
Preprint Aug 2026

A Thread-Register Decoupled GPU Execution Model for Efficient Tensor Computation

This work proposes FIBER, a new architecture that extends the GPU SIMT (single instruction, multiple thread) model, and extends the ISA, microarchitecture, and compiler to realize shared-register addressing, conflict-free operand delivery, and fiber-based program mapping.

Zi-Han Liu, Jingwen Leng, Yang-Jie Zhou et al. · 0 citations
Jul 2026

GPU-Tile-Sim: A Tile-Centric GPU Simulation Framework for LLM Hardware-Software Co-Design

This work proposes GPU-Tile-Sim, a tile-centric GPU simulation framework for LLM hardware-software co-design that represents kernel execution as a warp-level tile graph whose nodes capture tile-level operations and whose edges encode data and ordering constraints.

Yitong Ding, Jiawei Huang, Renyang Guan et al. · 2 citations

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