Fully Homomorphic Encryption (FHE) enables privacy-preserving cloud services but incurs substantial computation overhead, making hardware acceleration essential. Among FHE operations, key-switching is a major performance bottleneck. Recent cryptographic advances introduce a novel key-switching method (i.e., KLSS) that reduces certain operational complexity but demands higher computational precision than the traditional Hybrid Key Switching (HKS) method. This trade-off leads to distinct computation and memory requirements, making the relative latency of KLSS and HKS highly dependent on hardware parallelism, FHE security parameters, and available on-chip memory capacity, particularly on FPGA platforms, where memory resources and parallelism must be carefully balanced. In this work, we first propose a memory-efficient KLSS datapath that eliminates off-chip ciphertext transfers. We then develop a performance model to analyze and compare the overheads of both KLSS and HKS. Our analysis reveals that an adaptive solution supporting both methods can achieve lower overall latency than a static method during FHE computation. Guided by the performance model, we design an adaptive FPGA-based FHE accelerator that dynamically selects between HKS and KLSS during computation. We implement the accelerator on an Alveo U280 and evaluate it across multiple FHE benchmarks. Experimental results demonstrate that our adaptive solution achieves a 1.84-3.31$\times$ speedup in bootstrapping latency and a 1.66-2.52$\times$ speedup in secure image classification compared to state-of-the-art FPGA accelerators.
Zhi-Han Xu, Jayashree Adivarahan, Rajgopal Kannan et al.· 0 citations
Homomorphic Encryption (HE) enables secure computation on encrypted data, addressing privacy concerns in cloud computing. However, the high computational cost of HE operations, particularly matrix multiplication (MM), remains a major barrier to its practical deployment. Accelerating Homomorphic Encrypted MM (HE MM) is crucial for applications such as privacy-preserving machine learning. In this paper, we present S2MM, the first scalable FPGA-based accelerator designed for HE MM. We show that HE MM is fundamentally bottlenecked by excessive off-chip memory traffic when operating with practical HE parameter sets. To analyze this bottleneck, we develop a cost model that characterizes the on-chip memory requirements of ciphertexts during HE MM, revealing the scalability limits of CPU-based implementations. Guided by the analysis, we propose a novel datapath for Homomorphic Linear Transformation (HLT), the dominant workload in HE MM. The proposed datapath enables fine-grained on-chip data reuse, substantially reducing both off-chip memory traffic and on-chip memory demand. To further improve scalability, S2MM supports tiled HE MM, removing the matrix size limitation imposed by the HE encoding capacity and enabling efficient computation on large matrices. In addition, the architecture is highly configurable, adapting to diverse matrix sizes and HE parameter sets while maximizing throughput within FPGA resource constraints. We also introduce a systematic configuration methodology to determine optimal design parameters for efficient deployment across varying workloads and platforms. We implement S2MM on an Alveo U280 and conduct comprehensive evaluations across a wide range of matrix sizes, shapes, and HE parameters. Experimental results demonstrate that S2MM achieves average speedups of 219× and 37.4× over state-of-the-art CPU and GPU implementations, respectively. We further evaluate S2MM in an application-level encrypted CNN inference pipeline, achieving a 6.08× end-to-end speedup by accelerating the HE MM-dominated fully connected layers.
Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna· ACM Transactions on Reconfig...· 0 citations
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