Author

Yangdi Lyu

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Preprint Aug 2026

MiCoPro: End-to-End Mixed Precision HW/SW Co-design with HW-aware Proxy Model

The MiCo framework is proposed, a holistic MPQ exploration and deployment framework for edge AI applications that adopts a novel optimization algorithm to search for accuracy-optimal quantization configurations under strict latency constraints and is extended to MiCoPro, which introduces a robust Hardware-Aware Proxy m...

Zijun Jiang, Yangdi Lyu · 0 citations

Review Jul 2026

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

ChipVerilog is presented, a description-to-Verilog generation benchmark built from OpenCores IP/core designs that shows that large-scale RTL remains challenging, especially for hierarchical and cross-module designs.

Yan Tan, Jiping Du, Xiangchen Meng et al. · arXiv.org · 1 citation