Open access
2026
A 10-bit Synchronous SAR ADC with Dynamic Clock Phase Generation for Ultra-Low Power Mixed-Signal Applications in 45nm CMOS
A dynamic, low-power SAR ADC optimized for low-power mixed-signal applications using 45nm CMOS technology and a modular “divide-and-conquer” verification strategy is implemented to ensure functional correctness and performance reliability.
Y. Wong
· Jordan journal of electrical... · 0 citations