Author

Xiangchen Meng

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Review Jul 2026

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

ChipVerilog is presented, a description-to-Verilog generation benchmark built from OpenCores IP/core designs that shows that large-scale RTL remains challenging, especially for hierarchical and cross-module designs.

Yan Tan, Jiping Du, Xiangchen Meng et al. · arXiv.org · 1 citation