Author

U. R. Tida

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Preprint Aug 2026

AgentDV: Closed-Loop Agentic AI for Hardware Design Verification

AgentDV is presented, a closed-loop agentic AI framework for automated RTL verification environment generation that transforms single-shot LLM testbench generation into a tool-grounded verification pipeline by combining LLM-guided analysis, testbench construction, simulation, coverage measurement, and iterative refinement.

Navya Goli, Junzhe Liu, Zhen-Ge Jia et al. · 0 citations