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Shuqing Zhao

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Jul 2026

Formally Verified Synthesizable Floating-Point Data Types in ARCH HDL

We report the design and end-to-end verification of first-class IEEE-754 binary32 (FP32) and bfloat16 (BF16) arithmetic for ARCH, a hardware description language intended to be generated by language models. Every operator - comparisons, conversions, add, sub, mul, and fused multiply-add (FMA) - is described once agains...

Shu-Qing Zhao · arXiv.org · 0 citations